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When Should A Pad Use Window-Pane Paste Mask?

Printed From: PCB Libraries Forum
Category: Libraries
Forum Name: Footprints / Land Patterns
Forum Description: [General or a CAD specific issues / discussions]
URL: http://www.PCBLibraries.com/forum/forum_posts.asp?TID=2600
Printed Date: 26 Feb 2021 at 8:58pm


Topic: When Should A Pad Use Window-Pane Paste Mask?
Posted By: SWB01
Subject: When Should A Pad Use Window-Pane Paste Mask?
Date Posted: 31 Jan 2020 at 10:24pm
Is there a rule of thumb for determining when a pad should have window-pane, or otherwise reduced, solder paste?

I occasionally come across parts with thermal pads – and/or simply very large bottom-termination pads – where there is no paste recommendation in the datasheet – or in some cases, not even a basic land-pattern recommendation, or one that is obviously sub-optimal. One example (but not the only one) is high-power Chinese LED's with low-information datasheets.

Absent a recommendation from the manufacturer, how do I decide whether a particular pad should have reduced solder paste, either through window-pane or simply shrinking the paste mask, and if it should, by how much the paste should be reduced? Is it based on the absolute pad size (e.g. any pads larger than x should be paste-reduced), or maybe based on the size of the pad relative to the size of the part or something?

The particular part I'm working on at the moment is a 5.7×3.0 mm LED in a package much like a small-outline diode flat lead (SODFL), except it has a 2.7×2.0 mm thermal pad underneath it.



Replies:
Posted By: Tom H
Date Posted: 01 Feb 2020 at 9:36am
Typically, the thermal pad paste mask is reduced between 40 - 60%. 

The exception is when the thermal pad width is less than 1.00 mm, then window-pane is not necessary because the solder paste is low volume. 

read this:  https://www.pcblibraries.com/forum/paste-mask-rules-for-thermal-pads_topic2452.html" rel="nofollow - https://www.pcblibraries.com/forum/paste-mask-rules-for-thermal-pads_topic2452.html



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Posted By: SWB01
Date Posted: 01 Feb 2020 at 2:11pm
So are you saying that any bottom-terminated pad with X and Y dimensions both 1.00 mm should be treated as a thermal pad and window-paned? And conversely, any bottom-terminated pad with at least one dimension <1.00 mm should not be window-paned and have a paste aperture equal to the pad size and shape?


Posted By: Tom H
Date Posted: 01 Feb 2020 at 2:21pm
Only pads that are designated as "Thermal Pads" that require vias to a GND plane to reduce heat. 

Thermal Pads less than 1.00 mm wide would require small paste mask apertures. 

However, Some manufacturer's like Texas Instruments still reduce the paste mask on thermal pads less than 1.00 mm width. 

In this example, the paste mask apertures are 0.84 (same as the pad width) X 1.00 mm with a 0.20 mm gap. 83% paste coverage. 



I recommend that if the mfr. provides this type of detail, you should probably use it. 



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Posted By: SWB01
Date Posted: 01 Feb 2020 at 4:27pm
Originally posted by Tom H Tom H wrote:

Only pads that are designated as "Thermal Pads" that require vias to a GND plane to reduce heat.

What about thermal pads where I'm not using vias to ground? (Examples: LEDs on a single-layer aluminum board. Or even a part on a 2- or 4-layer board where I opt not to include the vias to ground for whatever reason. [Maybe I know the part won't get hot and I choose to omit them for routing reasons. Maybe the thermal pad, while large compared to the other pins on the part, is nevertheless too small to reasonably accommodate a via unless I plug it or something.])

I gather that having too much solder under a large bottom-termination pad may cause the part to float during reflow, potentially resulting in shorts, or perhaps lifting other pins from their pads and resulting in no connection on those pins. I'm trying to understand how to identify when I might need to be worried about this and to reduce the paste on the large pad to compensate.


Originally posted by Tom H Tom H wrote:

I recommend that if the mfr. provides this type of detail, you should probably use it.

Sure, but the issue I run into occasionally is that the manufacturer doesn't provide this information, which is part of the reason I'm asking. (Example: Low-information datasheets for no-name Chinese parts.)

Another reason is to have enough background knowledge to do a sanity check on what the manufacturer is recommending in cases where they do present a recommendation. (For example, I've seen instances of parts with very large thermal pads where the manufacturer-recommended footprint shows full solder-paste under the pad, with no window-paning or other paste reduction. This seems wrong. But I don't know enough about it to say for sure.)


Posted By: Tom H
Date Posted: 01 Feb 2020 at 4:40pm
The Paste Mask reduction is specifically used to prevent the package from sitting on top of a large blob of solder to prevent rocking or teeter-totter so that one side of the package is up in the air due to the solder migration to one side or the other. 

You can also solder mask define the thermal pad to prevent solder in vias and reduce or eliminate solder voids due to window-pane. 

Read this:  https://www.pcblibraries.com/forum/ipc7093a-btc-qfn-solder-mask-defined-thermal-pad_topic2154.html" rel="nofollow - https://www.pcblibraries.com/forum/ipc7093a-btc-qfn-solder-mask-defined-thermal-pad_topic2154.html



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Posted By: SWB01
Date Posted: 01 Feb 2020 at 5:40pm

I understand, but what Im trying to work out is:

I have a part with one or more large bottom-termination pads, according to some unknown definition of large, that may or may not be intended or actually used as a thermal pad.

The part probably also has some number of non-bottom-termination pads. Perhaps gull-wing style, perhaps flat-lead style, or something else.

Importantly, I do not have a recommended land pattern. (Or even if I do, the pattern is deemed untrustworthy for some reason. Maybe it has obvious errors.)

 

Under these circumstances, what rules do I use to decide which pads, if any, should have a reduced paste mask (regardless of the method used to achieve this), and by how much the mask should be reduced?

It seems there must be some formulas or rules of thumb used to balance the solder load applied to the various pads of an arbitrary package design. After all, how do the manufacturers (the ones that provide high-quality, complete documentation) determine this? Is it pure trial-and-error based on testing? Isn't there some basic theory that gets them close on the first try?

Would it be incorrect, as a rule of thumb, and in the absence of a more authoritative recommendation, to automatically reduce the solder mask for bottom-termination center pads that exceed 1.00 mm in both dimensions to about 50% (based on your first response above)?



Posted By: Tom H
Date Posted: 01 Feb 2020 at 6:28pm
Thermal Tabs do not have a Toe, Heel or Side fillet for the solder to flow. Typically, the thermal tab and the pad are the same Nominal size. 

The basic principle is that your goal is to have even paste distribution on all pads after the reflow oven. 

Let's say you use a 0.125 mm (5 mil) stencil thickness. If you have a thermal pad that has 100% paste mask coverage, there is no where for the solder to flow and the package ends up sitting on top of 0.125 mm of solder while all the signal pins have a Toe, Heel and Side for the solder to migrate to. 

After reflow, the solder under a signal terminal is 0.05 mm because the hot solder runs out to the Toe, Heel and Side fillet. But the thermal tab is floating on 0.125 mm of solder. 

The rule is simple. If the terminal lead pad does not have a Toe, Heel and Side fillet then it requires paste mask reduction so that the final result post reflow oven is about 0.05 mm solder thickness to match the signal pad solder thickness under the terminal lead. 



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Posted By: SWB01
Date Posted: 02 Feb 2020 at 8:36pm
Perfect; thank you! That's exactly the information I was looking for.



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