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Footprints for High Vibration and Shock

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    Posted: 06 Nov 2019 at 2:46am
Hi Everyone,

I was wondering if there are any standards or guidelines for designing footprints to withstand mechanical shocks and vibration?

I've read through all the Land Pattern Expert documentation, IPC 7351b and anything else I can find but the focus tends to be on a footprint's suitability for assembly and manufacture rather than withstanding mechanical stress during operation.

Ideally I'm looking for a standard or study relating component size and copper pad area to vibration/shock withstand.

I'm aware of other design techniques to mitigate vibration/shock susceptibility, I'm really just interested in knowing if there's been any work in this area for PCB SMT footprints.

Cheers,
-Tom
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 06 Nov 2019 at 7:03am
Originally, the IPC-7351 Most Density was the solution for high shock and vibration, but 8 years ago the Japanese did tests on the Nominal and Most Density Levels and discovered that there was no difference between the two levels. The Nominal Density Level held up to all the tests and the Most Density Level was obsoleted in the Japanese industry as it put too much solder on the joints. 

I do not know of a standard that defines mechanical shocks and vibration. But here is the link to the IPC standard tree of documents. 


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Post Options Post Options   Thanks (0) Thanks(0)   Quote tompope Quote  Post ReplyReply Direct Link To This Post Posted: 06 Nov 2019 at 8:07pm
Thanks Tom :)

Do you know if they publish any papers or test reports?
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 07 Nov 2019 at 7:46am
Not that I've seen. 

IPC gathers information from the global electronics industry and formalizes the data into documents that are called Standards or Guidelines. 

Most companies who run stress tests consider that investment confidential and proprietary and do not disclose that data to the public as it gives them a competitive edge in the industry. 

Also, I have never known IPC to run their own PCB fabrication and assembly for the purpose of evaluation of solder joints, stress and thermal cycle testing. That's not their business model and they don't have the expertise to run those tests and report their findings. 

Example: The IPC-7351 Land Pattern Guideline does not provide any proof that the solder joint goals really work. The goals were an educated guess by Dieter Bergman and other top employees and contributors of the 7351 Guideline, including myself. Now after 20 years on the Land Pattern Committee, I totally disagree with 7351 solder joint goals and I follow the IPC-J-STD-001 standard for land pattern calculation solder joint goals. 

I wish you the best of luck finding the test results you are looking for. 

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