This is an example of a 1206 Chip Resistor package. 

Dimensions: H = 1.40, D = 3.20 ±0.20, E = 1.60 ±0.20, L = 0.50 ±0.25

The IPC-7352 mathematical model includes the D, E and L dimensions and tolerances and the solder joint goal settings for Toe = 0.35, Heel = 0.00, Side = 0.00

Resulting pad size rounded to 2 places is – L 1.15 x W 1.80 x G 1.80

The resulting pad stack pattern must have the terminal leads on the pad stack in these conditions:

The Nominal Material condition of the component package & Nominal Terminal.

The Minimum Material condition of the component package & Nominal Terminal.

The Maximum Material condition of the component package & Nominal Terminal.

The Minimum Material condition of the component package & Minimum Terminal.

The Maximum Material condition of the component package & Maximum Terminal.

The resulting pad stack must have terminal leads on the pad stack regardless of every possible Material Condition possible to pass assembly inspection and meet the requirements set forth in the IPC J-STD-001 Standard and the IPC-7352 Guideline in Figure 3-3 Profile Dimensioning. 

i.e.: regardless of the Component Package and Terminal Lead Material Condition, the Terminal Lead must never be exposed outside the calculated pad stack. 

This is proof that the V24 Footprint Expert mathematical model illustrated in the IPC-7352 guideline achieves that goal. 

Note: most component packages are created in the Nominal Material Conditions. The package tolerances play a key role in the resulting pad stack. Nominal Package Dimensions & no Package Tolerances. 

Definitions:

(All dimensions are in millimeters)

tol = tolerance

min = minimum, max = maximum

L = lead span, S = lead space

T = terminal length, W = terminal width

Example for a 1206 Chip

Lmax = 3.40, Lmin = 3.00, Ltol = length tolerance = Lmax – Lmin = 0.40

Tmax = 0.75, Tmin = 0.25, Ttol = terminal tolerance = Tmax – Tmin = 0.50

Wmax = 1.80, Wmin = 1.40, Wtol = width tolerance = Wmax – Wmin = 0.40

Smax = Lmax – (2 * Tmin) = 3.40 – (2 * 0.25) = 2.90

Smin = Lmin – (2 * Tmax) = 3.00 – (2 * 0.75) = 1.50

Stol (worst case) = Smax – Smin = 2.9 – 1.5 = 1.40

The worst-case difference between ‘Smin’ and ‘Smax’, 1.40, is statistically improbable since a simutaneous combination of extreme material conditions is considered beyond the actual range within which components are manufactured. To arrive at a more realistic tolerance range, the RMS (Root Mean Square) value is calculated using the tolerances on the dimensions involved.  In this case ‘L’ and ‘T’.

Zmax = pad span, Gmin = pad space

Jt = toe goal (outside fillet)

Tt = Toe tolerance

Jh = heel goal (inside fillet), Js = side goal (fillet)

Ht = heel tolerance

RMS = Root Mean Square

F = fabrication tolerance, P = placement tolerance

Examplefor the 1206 Chip

PCB Footprint Expert

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Every aspect of a PCB mounted component has tolerances.These include tolerances for Package length/width and terminals. The IPC-7351B refers to amathematical model that also includes fabrication and assembly tolerances.IPC-7352 removed the manufacturing tolerances from the mathematical model.

The mathematical model takes into consideration the minimumand maximum package dimensions to ensure that the resulting land patternaccommodates the package tolerance range. Tolerances are referred to as Min/Maxtechnology meaning the pad stack size and spacing regardless of if thecomponent package comes in the minimum or maximum material condition.

Since the package and terminal tolerances affect theresulting pad stack size and spacing, robust tolerances will produce larger padstacks while no tolerances will produce pad stacks that are too small. The IPC-7351Side solder joint goal for chip packages is zero. The pad width is the samedimension as the Maximum terminal lead width.

The Heel solder joint goal for chip packages is zero. Theheel is determined by the terminal lead and package length tolerances.

The Toe normally has a solder joint goal has a predefinedvalue. Then the terminal lead and package length tolerances are added to theToe value. The resulting Toe solder joint is a combination of the Toe goalvalue and terminal and package length tolerances.

Here are the recommended tolerances for the various chipcase codes:

• 01005 – 0.02 mm
• 0201 – 0.03 mm
• 0402 – 0.05 mm
• 0603 – 0.10 mm
• 0805 – 0.15 mm
• 1206 and higher – 0.20 mm

Different component manufacturers will publish a wide rangeof tolerances. For example, Panasonic, Yageo, Vishay, AVX, Murata, Kemet andTaiyo Yuden will have different tolerances to the same Case Code. But the PCBdesigner or CAD librarian want one set of tolerances for each Case Code.

Here is a 0603 Chip with no tolerances: 

Here is a 0603 Chip with a 0.05 tolerance on Length, Widthand Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.10 tolerance on Length, Widthand Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.15 tolerance on Length, Widthand Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.20 tolerance on Length, Widthand Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.25 tolerance on Length, Widthand Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.10 tolerance on Length, Widthand Terminal Least Density Level:

Here is a 0603 Chip with a 0.10 tolerance on Length, Widthand Terminal Most Density Level:

Chip component manufacturers do not use their packagetolerances when publishing their manufacturer recommended patterns. They use nominalpackage dimensions and add a toe, heel and side solder joint regardless of howrobust their tolerances are. If component tolerances are real and componentpackages can be shipped to assembly shops and some come in the minimum materialcondition and some come in the maximum material condition, there will beassembly attachment issues.

PCB Footprint Expert

Simplify your PCB design process with the Footprint Expert, the ultimate tool - it can automatically rebuild entire libraries with modified tolerances. Automation helps ensures accurate, consistent, reliable footprints with minimal introduction of human error. Let the Footprint Expert handle your CAD library so you can focus on creating flawless PCB designs faster and more efficiently!