PCB Libraries Forum : PCB Library Construction Guidelines https://www.PCBLibraries.com/forum/ Thu, 09 Apr 2026 05:54:35 +0000 Fri, 28 Mar 2025 13:38:11 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 30 https://www.PCBLibraries.com/forum/RSS_topic_feed.asp?FID=30 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[PCB Library Construction Guidelines : IPC-7351 Collapsing and Non-Collapsing BGA Balls]]> https://www.PCBLibraries.com/forum/ipc7351-collapsing-and-noncollapsing-bga-balls_topic3370_post13843.html#13843 Author: Tom H
Subject: IPC-7351 Collapsing and Non-Collapsing BGA Balls
Posted: 28 Mar 2025 at 1:38pm

If the Ball diameter is on the dividing row between percentages the new ball size will take the lower values. 

Here is a sample BGA terminal option table where the 0.24 mm Ball Diameter was added.


 
]]> Fri, 28 Mar 2025 13:38:11 +0000 https://www.PCBLibraries.com/forum/ipc7351-collapsing-and-noncollapsing-bga-balls_topic3370_post13843.html#13843 <![CDATA[PCB Library Construction Guidelines : IPC-7351 Collapsing and Non-Collapsing BGA Balls]]> https://www.PCBLibraries.com/forum/ipc7351-collapsing-and-noncollapsing-bga-balls_topic3370_post13842.html#13842 Author: mking
Subject: IPC-7351 Collapsing and Non-Collapsing BGA Balls
Posted: 28 Mar 2025 at 11:39am

For the collapsing BGA ball with a diameter between the values listed what is appropriate reduction?

My example is a 0.242 mm diameter. Is the recommended reduction 15%, 20%, or 19.2% (linear interpolation)?
]]> Fri, 28 Mar 2025 11:39:16 +0000 https://www.PCBLibraries.com/forum/ipc7351-collapsing-and-noncollapsing-bga-balls_topic3370_post13842.html#13842 <![CDATA[PCB Library Construction Guidelines : Placement Courtyard Excess]]> https://www.PCBLibraries.com/forum/placement-courtyard-excess_topic3372_post13804.html#13804 Author: achico
Subject: Placement Courtyard Excess
Posted: 21 Feb 2025 at 12:27am

Thank you Tom for your clarifications and realistic industry point of view, much appreciated.

Best regards]]> Fri, 21 Feb 2025 00:27:21 +0000 https://www.PCBLibraries.com/forum/placement-courtyard-excess_topic3372_post13804.html#13804 <![CDATA[PCB Library Construction Guidelines : Placement Courtyard Excess]]> https://www.PCBLibraries.com/forum/placement-courtyard-excess_topic3372_post13800.html#13800 Author: Tom H
Subject: Placement Courtyard Excess
Posted: 20 Feb 2025 at 9:14am

IPC-7352 does not break down the courtyard to Pad and Body separately. 

The solder joint goal tables only refer to one courtyard Excess.
  • Least = 0.10
  • Nominal = 0.25
  • Most = 0.50
However, PCB Libraries customers think the Least value of 0.10 is OK, but then they double that for Nominal to 0.20 and then double that for Most to 0.40. Also, Siemens, Cadence and Zuken users turn off all Courtyard Excess values and use the courtyard as a placement boundary outline and they use internal CAD tool spacing rules for part placement. 

Both the Nominal and Most Density Levels pass all Class 3 stress tests for shock and vibration, thermal cycling and drop tests. So the Most Density is rarely used in production. But some mil spec contractors still use the Most Density Level, even though the Nominal Density Level performance is equal. But the Courtyard Excess values are user definable so some companies might use the Most pad stack calculation and a Nominal Courtyard Excess. 

The main point is that many PCB designers think outside the box and use IPC-7352 as a "Guideline" but don't use it verbatim. They glean some information from IPC but develop internal standards that work best with their assembly process. 

Another thing that many people don't understand is that IPC only offers guidelines for pad stacks and courtyard and don't have much information on all the elements that go into a footprint pattern. 

Here is an example of some things IPC does not provide guidelines and details for a typical land pattern: 


 

]]> Thu, 20 Feb 2025 09:14:44 +0000 https://www.PCBLibraries.com/forum/placement-courtyard-excess_topic3372_post13800.html#13800 <![CDATA[PCB Library Construction Guidelines : Placement Courtyard Excess]]> https://www.PCBLibraries.com/forum/placement-courtyard-excess_topic3372_post13799.html#13799 Author: achico
Subject: Placement Courtyard Excess
Posted: 20 Feb 2025 at 5:34am

From IPC-7352 I found this information, is it correct? It seems to be different as to IPC-7351B referenced.

IPC-7352 Courtyard Distances

Component TypeDensity LevelPad Edge to CourtyardComponent Body to Courtyard
SMD ComponentsA (Least Density)0.50 mm1.00 mm

B (Nominal Density)0.25 mm0.50 mm

C (Most Density)0.20 mm0.25 mm
Through-Hole ComponentsA (Least Density)0.75 mm1.25 mm

B (Nominal Density)0.50 mm1.00 mm

C (Most Density)0.25 mm0.50 mm
]]> Thu, 20 Feb 2025 05:34:27 +0000 https://www.PCBLibraries.com/forum/placement-courtyard-excess_topic3372_post13799.html#13799 <![CDATA[PCB Library Construction Guidelines : Why PCB Libraries Uses Different Standards]]> https://www.PCBLibraries.com/forum/why-pcb-libraries-uses-different-standards_topic3407_post13676.html#13676 Author: KoryJohnsonTek
Subject: Why PCB Libraries Uses Different Standards
Posted: 03 Oct 2024 at 10:12am

Hi Tom.  Thanks for the post.  I'm not a constant follower of the site, but do check in on occasion. I'm a bit curious about 7352 not including manufacturing tolerances.  Is there a backstory to that decision?]]> Thu, 03 Oct 2024 10:12:15 +0000 https://www.PCBLibraries.com/forum/why-pcb-libraries-uses-different-standards_topic3407_post13676.html#13676 <![CDATA[PCB Library Construction Guidelines : IPC-7351 & IPC-7352 Standard SMD Terminal Leads]]> https://www.PCBLibraries.com/forum/ipc7351-ipc7352-standard-smd-terminal-leads_topic3369_post13608.html#13608 Author: circuits
Subject: IPC-7351 & IPC-7352 Standard SMD Terminal Leads
Posted: 13 Aug 2024 at 6:39am

The IPC-7351 and IPC-7352 standards are essential guidelines for SMD (surface mount device) terminal leads, providing comprehensive recommendations for the design, placement and soldering of components on PCBs. These standards ensure consistency and reliability in the manufacturing process, which is crucial for maintaining product quality.

In my recent blog post on IPC Standards for PCB Manufacturing and Assembly, I examined these guidelines in more detail, including best practices for adhering to them in your designs. If you are interested in a deeper dive into how IPC standards can improve your PCB manufacturing and assembly processes, you may find it helpful.
]]> Tue, 13 Aug 2024 06:39:58 +0000 https://www.PCBLibraries.com/forum/ipc7351-ipc7352-standard-smd-terminal-leads_topic3369_post13608.html#13608 <![CDATA[PCB Library Construction Guidelines : Why PCB Libraries Uses Different Standards]]> https://www.PCBLibraries.com/forum/why-pcb-libraries-uses-different-standards_topic3407_post13597.html#13597 Author: Tom H
Subject: Why PCB Libraries Uses Different Standards
Posted: 05 Aug 2024 at 12:27pm

  • PCB Libraries, Inc. contributes and studies all the world standards for PCB library part rules. We only use the best practices from every standard. Examples:
    • IPC-7351B was the mathematical we used from 2005 – 2023
      • The mathematical model used manufacturing tolerances and negative solder joint goals to compensate for the manufacturing tolerances for side joints.
    • Footprint Expert changed to the IPC-7352 mathematical model in May 2023 when it was released
      • The mathematical model removed manufacturing tolerances and negative solder joint goals
      • However, users can revert to IPC-7351B if they want to use the old format
    • IPC J-STD-001 is used for solder joint goal guidelines. IPC-7351B and IPC-7352 guidelines for solder joint goals are too robust and do not adhere to J-STD-001 Standard.
    • IEC 61188-7 Level B is used for the default Pin 1 orientation.
      • IPC-SM-782 was the first surface mount standard released in 1987 and ran for 18 years. This standard matched the IEC 61188-7 Level B.
      • In 2005 IPC release 7351 and changed the Pin 1 orientation to Pin 1 Upper Left.
      • In 2007 IEC 61188-7 Level B was released to revert to the original orientation in IPC-SM-782
    • IPC-7351C is used for the footprint naming convention. 7351C was reviewed by the IPC Land Pattern Committee for 6 years. They approved the new naming convention, and we added it to Footprint Expert because it was superior to 7351B. Then IPC discontinued 7351C and never released it.
    • IPC-7352 is used for the pad stack naming convention.
    • FED Volume 18 by Rainer Taube released in 2018 supported Proportional Land Dimensioning Concept. It differs from IPC mathematical model that uses min/max package dimensions. The FED recommends using Nominal Package Dimensions and hard coding the solder joint goals for Toe, Heel and Side. Do not use package tolerances when using this concept and create realistic solder joint goals approved by your assembly shop.
    • Manufacturer’s Recommend Patterns are used for all non-standard packages and connectors

]]> Mon, 05 Aug 2024 12:27:15 +0000 https://www.PCBLibraries.com/forum/why-pcb-libraries-uses-different-standards_topic3407_post13597.html#13597 <![CDATA[PCB Library Construction Guidelines : PCB Design Optimization Starts in the CAD Library]]> https://www.PCBLibraries.com/forum/pcb-design-optimization-starts-in-the-cad-library_topic468_post13516.html#13516 Author: WilliamsimC
Subject: PCB Design Optimization Starts in the CAD Library
Posted: 19 Apr 2024 at 2:45am

Starting to make the PCB design better begins with the CAD library.

This is where we keep all the parts we'll use to build the design.

Making sure these parts are right is super important because they're like the building blocks of our project.

When we pick and set up the parts in the library, it helps us make the design process smoother, fix any signal problems, and stop mistakes early on.

Also, having a neat CAD library helps us keep things consistent in our designs, lets us reuse parts that work well, and makes it easier for us to work together as a team.

So, spending time to make sure our CAD library is in good shape is a smart move for making awesome PCB designs.

]]> Fri, 19 Apr 2024 02:45:12 +0000 https://www.PCBLibraries.com/forum/pcb-design-optimization-starts-in-the-cad-library_topic468_post13516.html#13516 <![CDATA[PCB Library Construction Guidelines : IEC 61188-7 Zero Component Orientations]]> https://www.PCBLibraries.com/forum/iec-611887-zero-component-orientations_topic3374_post13492.html#13492 Author: Tom H
Subject: IEC 61188-7 Zero Component Orientations
Posted: 07 Apr 2024 at 3:19pm

IEC 61188-7 International Standard for Zero Component Orientation. 

The zero orientation with pin 1 in the upper left corner was published in the IPC-7351A in 2007 and is referred to as “Level A”.




The zero orientation with pin 1 in the lower left corner was published in IEC 61188-7 in 2009 and is referred to as “Level B”.




Note: Level B is recommended as standard for new ECAD libraries for 3 reasons. 


1. For 18 years the original IPC-SM-782 used Level B. 


2. The footprint should be long in the horizontal due to computer screen shapes and ANSI and IEC paper sizes. 


3. PCB layouts are long in the horizontal to fit properly on the standard paper sizes.

 
]]> Sun, 07 Apr 2024 15:19:08 +0000 https://www.PCBLibraries.com/forum/iec-611887-zero-component-orientations_topic3374_post13492.html#13492