<?xml version="1.0" encoding="utf-8" ?>
<?xml-stylesheet type="text/xsl" href="RSS_xslt_style.asp" version="1.0" ?>
<rss version="2.0" xmlns:WebWizForums="https://syndication.webwiz.net/rss_namespace/">
 <channel>
  <title>PCB Libraries Forum : Pin 1 definition Vs Tape&amp;Reel format</title>
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  <description><![CDATA[This is an XML content feed of; PCB Libraries Forum : Footprints / Land Patterns : Pin 1 definition Vs Tape&amp;Reel format]]></description>
  <pubDate>Wed, 15 Apr 2026 23:30:46 +0000</pubDate>
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  <docs>http://blogs.law.harvard.edu/tech/rss</docs>
  <generator>Web Wiz Forums 12.07</generator>
  <ttl>360</ttl>
  <WebWizForums:feedURL>https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=938</WebWizForums:feedURL>
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  </image>
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   <title><![CDATA[Pin 1 definition Vs Tape&amp;Reel format :  There is a standard that you...]]></title>
   <link>https://www.PCBLibraries.com/forum/pin-1-definition-vs-tapereel-format_topic938_post3540.html#3540</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 938<br /><strong>Posted:</strong> 20 May 2013 at 6:48am<br /><br />There is a standard that you can search for EIA-481-D-2008m however the biggest problem is that only a small number of component manufacturer's use it. IPC and PCB Libraries, Inc. did research on this for the IPC-7351A and discovered that even the same component manufacturer breaks the Zero Component Orientation rules. So IPC established their own Zero Component Orientation (ZCO)&nbsp;for Footprint library parts. Then is 2007 IEC released their own Zero Component Orientation which was rotated 90 degrees from IPC. I explain&nbsp;EIA, IPC and IEC ZCO&nbsp;in this presentation - PCB Design Optimization Starts in the CAD Library available here - <a href="http://www.pcblibraries.com/forum/pcb-design-optimizati&#111;n-starts-in-the-cad-library_topic468.html" target="_blank" rel="nofollow">http://www.pcblibraries.com/forum/pcb-design-optimization-starts-in-the-cad-library_topic468.html</a><div>&nbsp;</div><div><span style='font-family: "Verdana","sans-serif"; font-size: 10pt; mso-bidi-font-family: "Times New Roman"; mso-bidi-font-weight: bold;'><strong>EIA-481-D</strong> - 8 mm THROUGH 200 mm </span><span style='font-family: "Verdana","sans-serif"; font-size: 10pt; mso-bidi-font-family: "Times New Roman"; mso-bidi-font-weight: bold;'>EMBOSSED CARRIER TAPING AND </span><span style='font-family: "Verdana","sans-serif"; font-size: 10pt; mso-bidi-font-family: "Times New Roman"; mso-bidi-font-weight: bold;'>8 mm &amp; 12 mm PUNCHED CARRIER </span><span style='font-family: "Verdana","sans-serif"; font-size: 10pt; mso-bidi-font-family: "Times New Roman"; mso-bidi-font-weight: bold;'>TAPING OF SURFACE MOUNT </span><span style='font-family: "Verdana","sans-serif"; font-size: 10pt; mso-bidi-font-family: "Times New Roman"; mso-bidi-font-weight: bold;'>COMPONENTS FOR AUTOMATIC </span><span style='line-height: 115%; font-family: "Verdana","sans-serif"; font-size: 10pt; mso-bidi-font-family: "Times New Roman"; mso-bidi-font-weight: bold;'>HANDLING.</span><span style='line-height: 115%; font-family: "Verdana","sans-serif"; font-size: 10pt;'><?: prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></span></div><div><font size="3" face="Times New Roman"></font></div>]]>
   </description>
   <pubDate>Mon, 20 May 2013 06:48:26 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/pin-1-definition-vs-tapereel-format_topic938_post3540.html#3540</guid>
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   <title><![CDATA[Pin 1 definition Vs Tape&amp;Reel format : Hi Tom,   Thanks for your reply...]]></title>
   <link>https://www.PCBLibraries.com/forum/pin-1-definition-vs-tapereel-format_topic938_post3539.html#3539</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=19">Nightwish</a><br /><strong>Subject:</strong> 938<br /><strong>Posted:</strong> 19 May 2013 at 11:05pm<br /><br />Hi Tom, <DIV>&nbsp;</DIV><DIV>Thanks for your reply on this. I know we can easily rotate cell when creating it but I want to know if the zero rotation of land pattern has something to do with the package type in tape &amp; reel. In Footprint Expert the default Orientation Pin 1 for TO part is down and for SOP it is left, is this an IPC standard?</DIV><DIV>&nbsp;</DIV><DIV>Thanks,</DIV><DIV>&nbsp;</DIV><DIV>Nightwish</DIV>]]>
   </description>
   <pubDate>Sun, 19 May 2013 23:05:02 +0000</pubDate>
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   <title><![CDATA[Pin 1 definition Vs Tape&amp;Reel format :  The PCB Footprint Expert (FPX)allows...]]></title>
   <link>https://www.PCBLibraries.com/forum/pin-1-definition-vs-tapereel-format_topic938_post3537.html#3537</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 938<br /><strong>Posted:</strong> 17 May 2013 at 6:21am<br /><br />The PCB Footprint Expert (FPX)&nbsp;allows you to output every library part in any rotation you want. <div>&nbsp;</div><div>On Monday, IPC will submit a Press Release to all news publications that they are now shipping FPX Lite with the purchase of the IPC-7351 Land Pattern standard. </div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Fri, 17 May 2013 06:21:56 +0000</pubDate>
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   <title><![CDATA[Pin 1 definition Vs Tape&amp;Reel format : These days I created a cell for...]]></title>
   <link>https://www.PCBLibraries.com/forum/pin-1-definition-vs-tapereel-format_topic938_post3533.html#3533</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=19">Nightwish</a><br /><strong>Subject:</strong> 938<br /><strong>Posted:</strong> 16 May 2013 at 10:39pm<br /><br /><P>These days I created a cell for a connector and the Pin 1 is set on lowwer left while our DFME set the pin 1 on top in his VPL library. I am not sure if IPC has this kind of definition on how to define pin 1 according to component package in tape&amp;reel? Picture below shows the snap shot of the tape&amp;reel format.</P><DIV>&nbsp;</DIV><DIV><img src="http://www.pcblibraries.com/Forum/uploads/19/Untitled.png" height="368" width="459" border="0" /></DIV><DIV><img src="http://www.pcblibraries.com/Forum/uploads/19/Untitled1.png" height="516" width="172" border="0" />&nbsp;&nbsp; Cell</DIV><DIV>&nbsp;</DIV><DIV>Thanks,</DIV><DIV>&nbsp;</DIV><DIV>Nightwish</DIV>]]>
   </description>
   <pubDate>Thu, 16 May 2013 22:39:35 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/pin-1-definition-vs-tapereel-format_topic938_post3533.html#3533</guid>
  </item> 
 </channel>
</rss>