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   <title><![CDATA[Proportional Through-hole Padstacks : Thanks a lot for sharing this...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post8089.html#8089</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=11980">laiDennis</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 23 Sep 2016 at 12:45am<br /><br /><font><font><img src="https://www.PCBLibraries.com/forum/smileys/smiley1.gif" border="0" alt="微笑" title="微笑" /><span style="color: rgb34, 34, 34; font-family: arial; font-size: 13.3333px; text-align: justify;">Thanks a lot for sharing this with us</span></font></font>]]>
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   <pubDate>Fri, 23 Sep 2016 00:45:53 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post8089.html#8089</guid>
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   <title><![CDATA[Proportional Through-hole Padstacks :    Please download the latest...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1954.html#1954</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1">Nick B</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 04 Oct 2012 at 3:26pm<br /><br />Please download the latest PTH Padstack Reference Calculator from <a href="http://www.pcblibraries.com/forum/forum_posts.asp?TID=596" target="_blank" rel="nofollow">HERE</a>.<div>&nbsp;</div>]]>
   </description>
   <pubDate>Thu, 04 Oct 2012 15:26:44 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1954.html#1954</guid>
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   <title><![CDATA[Proportional Through-hole Padstacks :  IPC-7251_Padstack_Charts.xlsDear...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1948.html#1948</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=60">Vladimir.Stoyanov</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 03 Oct 2012 at 9:46pm<br /><br /><a href="uploads/60/IPC-7251_Padstack_Charts.xls" target="_blank" rel="nofollow">IPC-7251_Padstack_Charts.xls</a><br><br>Dear Tom,<br>Now I see that I can attach a file. I just asked you for update of this table. I don't want to use Least neither Nominal level for PTH. Can you help me?<br>Kind regards,<br>]]>
   </description>
   <pubDate>Wed, 03 Oct 2012 21:46:52 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1948.html#1948</guid>
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   <title><![CDATA[Proportional Through-hole Padstacks :   All of the latestupdated tables,...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1940.html#1940</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 03 Oct 2012 at 7:01am<br /><br />All of the latest&nbsp;updated tables, charts and rules are for free download here - <a href="http://www.pcblibraries.com/forum/pcb-library-c&#111;nstructi&#111;n-guidelines_forum30.html" target="_blank" rel="nofollow">http://www.pcblibraries.com/forum/pcb-library-construction-guidelines_forum30.html</a><div>&nbsp;</div><div>Or here - </div><div><a href="http://www.pcblibraries.com/Downloads/" target="_blank" rel="nofollow">http://www.pcblibraries.com/Downloads/</a>&nbsp;</div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Wed, 03 Oct 2012 07:01:45 +0000</pubDate>
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   <title><![CDATA[Proportional Through-hole Padstacks : Dear Tom,I made terrible mistake...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1937.html#1937</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=60">Vladimir.Stoyanov</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 02 Oct 2012 at 11:49pm<br /><br />Dear Tom,<br>I made terrible mistake - for PTH I use Most level, not Least. Even with this level I receive a mumble from our plants. For PTH footprints I use Excel table from PCB Matrix, but it is quite old. Do you have an update of this table?<br><br><img src="" border="0" /><br><br>Thanks a lot!<br>]]>
   </description>
   <pubDate>Tue, 02 Oct 2012 23:49:51 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1937.html#1937</guid>
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   <title><![CDATA[Proportional Through-hole Padstacks :   The PCB Footprint Expert supports...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1934.html#1934</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 02 Oct 2012 at 7:23am<br /><br />The PCB Footprint Expert supports the unreleased IPC-7251 through-hole standard but I prefer "Proportional Padstacks" because they cover all 3-Tiers. <div>&nbsp; </div><div>The IPC-7251 has fixed annular rings for each tier, regardless of the hole size. </div><div>&nbsp; </div><div>The Proportional Padstack annular ring gradually increases with the hole size. So small holes use the Least annular ring, medium size holes use Nominal annular ring and larger hole sizes use the Most annular ring. Then there's a point where the hole size is larger than 2 mm (80 mils) and the annular ring gradually gets even larger than the IPC-7251 standard. </div><div>&nbsp; </div><div>So Proportional Padstacks meet or beat IPC-7251. The theory is simple. If a through-hole component lead has a large diameter it's for a reason. It might need to carry a lot of current or the component may be tall and requires stability or the component may be heavy and require support. All of these reasons require a larger annular ring which allows more solder. </div><div>&nbsp; </div><div>Example: in the case of a large component lead that carries current, this will increase the temperature as the board functions and the large annular dissipates heat. If you use the Least Environment with the small annular ring, it's less solder and less heat dissipation. </div><div>&nbsp; </div><div>Note: I've used the Proportional Padstacks on over 1,000 PCB layout designs for both prototype and production boards and never had a manufacturing problem or a field problem. It's proven to be a very reliable padstack. </div><div>&nbsp; </div><div>Here is the IPC-7251 table for Axial Lead components: </div><div>&nbsp;</div><div><img src="uploads/3/IPC-7251_Axial_Lead_Table.png" height="700" width="577" border="0" /></div><div>&nbsp;</div>]]>
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   <pubDate>Tue, 02 Oct 2012 07:23:06 +0000</pubDate>
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   <title><![CDATA[Proportional Through-hole Padstacks :  Hi Tom,Do you release the through-hole...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1931.html#1931</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=60">Vladimir.Stoyanov</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 01 Oct 2012 at 11:41pm<br /><br />Hi Tom,<div>&nbsp;</div>Do you release the through-hole component families to select from IPC 7251 3-Tier? <div>&nbsp;</div>I prefer to use Least level for all my PTH components.<div>&nbsp;</div>Regards,<br> ]]>
   </description>
   <pubDate>Mon, 01 Oct 2012 23:41:43 +0000</pubDate>
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   <title><![CDATA[Proportional Through-hole Padstacks :   Mounting Holes will not make...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1925.html#1925</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 01 Oct 2012 at 11:54am<br /><br />Mounting Holes will not make it into the PCB Footprint Expert. <div>&nbsp;</div><div>All ANSI and ISO Mounting Holes will be available in every CAD format for free download soon. </div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Mon, 01 Oct 2012 11:54:19 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1925.html#1925</guid>
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   <title><![CDATA[Proportional Through-hole Padstacks : The Footprint names for Mounting...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1924.html#1924</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=91">plinder</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 01 Oct 2012 at 10:43am<br /><br />The Footprint names for Mounting Holes look different than the last version of LP Wizard.&nbsp; What naming convention do you plan on carrying forward for Mounting Holes?]]>
   </description>
   <pubDate>Mon, 01 Oct 2012 10:43:05 +0000</pubDate>
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   <title><![CDATA[Proportional Through-hole Padstacks :   I have heard from Gary Ferrariat...]]></title>
   <link>https://www.PCBLibraries.com/forum/proportional-throughhole-padstacks_topic90_post1535.html#1535</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 90<br /><strong>Posted:</strong> 21 Aug 2012 at 9:10am<br /><br />I have heard from Gary Ferrari&nbsp;at this years IPC APEX conference&nbsp;that the IPC-2221 and 2222 are being overhauled and will be released before the next IPC APEX conference in San Diego, CA in early 2013. But I don't see any release notification here - <a href="http://www.ipc.org/CommitteeDetail.aspx?Committee=D-31B" target="_blank" rel="nofollow">http://www.ipc.org/CommitteeDetail.aspx?Committee=D-31B</a><div>&nbsp;</div><div>All I can say is that the Proportional Via Padstacks have been used in production by CADPRO on over 2,000 PCB layouts and Wind River (now Intel)&nbsp;and all their PCB Layouts before we released it to the public in 2004 via PCB Libraries, Inc. </div><div>&nbsp;</div><div>No fabrication shop or EE engineer has ever complained of problems and many of the designs we did went into high volume production. </div><div>&nbsp;</div><div>Download the paper on PCB Design Optimization Starts in the CAD Library -</div><div><a href="http://www.pcblibraries.com/forum/pcb-library-optimizati&#111;n-presentati&#111;n-free_topic468.html" target="_blank" rel="nofollow">http://www.pcblibraries.com/forum/pcb-library-optimization-presentation-free_topic468.html</a>&nbsp;</div><div>&nbsp;</div><div>Here is a picture from the presentation regarding inner layer shifting &amp;&nbsp;annular ring&nbsp;- </div><div>&nbsp;</div><div><img src="uploads/3/Layer_Stackup_Via.png" height="284" width="718" border="0" /></div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Tue, 21 Aug 2012 09:10:26 +0000</pubDate>
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