<?xml version="1.0" encoding="utf-8" ?>
<?xml-stylesheet type="text/xsl" href="RSS_xslt_style.asp" version="1.0" ?>
<rss version="2.0" xmlns:WebWizForums="https://syndication.webwiz.net/rss_namespace/">
 <channel>
  <title>PCB Libraries Forum : SMT Headers</title>
  <link>https://www.PCBLibraries.com/forum/</link>
  <description><![CDATA[This is an XML content feed of; PCB Libraries Forum : Questions &amp; Answers : SMT Headers]]></description>
  <pubDate>Fri, 29 May 2026 09:54:06 +0000</pubDate>
  <lastBuildDate>Wed, 23 Jan 2013 02:21:09 +0000</lastBuildDate>
  <docs>http://blogs.law.harvard.edu/tech/rss</docs>
  <generator>Web Wiz Forums 12.07</generator>
  <ttl>360</ttl>
  <WebWizForums:feedURL>https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=736</WebWizForums:feedURL>
  <image>
   <title><![CDATA[PCB Libraries Forum]]></title>
   <url>https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif</url>
   <link>https://www.PCBLibraries.com/forum/</link>
  </image>
  <item>
   <title><![CDATA[SMT Headers : Thanks Tom, I only did this in...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2921.html#2921</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=53">jameshead</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 23 Jan 2013 at 2:21am<br /><br />Thanks Tom,&nbsp; I only did this in this one case to find out what pad styles would be needed to be added to a technology file.&nbsp; No intention of using it for anything proper.]]>
   </description>
   <pubDate>Wed, 23 Jan 2013 02:21:09 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2921.html#2921</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers :   I want to warn everyone never...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2919.html#2919</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 22 Jan 2013 at 11:32am<br /><br />I want to warn everyone never to use FPE FPX to Batch Create a library. There are thousands of parts with different Thermal Tab sizes and Lead tolerances with the same Footprint Name. As an example, just look at the duplicate footprint names&nbsp;in the "Intersil" CM section. <div>&nbsp;</div><div><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt; text-align: center;" ="Ms&#111;normal" align="center"><b style="mso-bidi-font-weight: normal;"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 20pt;'>FPXDisclaimer<?: prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></span></b></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>The FPE FPX file is to be used as “Reference only”. Itshould never be considered as a “Starter Library”. <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>PCB Libraries, Inc. is not responsible for componentdimensional typographical errors. It’s up to each user to verify everycomponent dimension with the corresponding mfr. datasheet to insure that all ofthe dimensions match. If you find a dimension that is not correct, pleasereport it immediately to <a href="mailto:support@pcblibraries.com" target="_blank" rel="nofollow"><u><font size="2" face="Tahoma">support@pcblibraries.com</font></u></a>and we’ll fix the error immediately. <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>There are hundreds of footprints that have the sameidentical name with different tolerances and thermal pad sizes. The FPE FPXfile is intended to be used as a library source for users to quickly locate thecorrect component package data row and copy/paste that row from FPE FPX intoyour personal library. When doing so, it’s up to you the user to rename thefootprint to avoid duplicate footprint names with tolerance and thermal paddifferences. <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>There is no guidance from IPC at this time on how tohandle variations in Thermal Tab sizes. One of the recommendations PCBLibraries, Inc. has for various thermal pad sizes is to append the end of thefootprint name with underscore _ and “T” (for Thermal) and the component TabSize. <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>Examples:<o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>QFN50P600X600X100-41rename to <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>QFN50P600X600X100-41<b style="mso-bidi-font-weight: normal;">_T365</b> = Thermal Tab size is 3.65 mmsquare <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>QFN50P600X600X100-41<b style="mso-bidi-font-weight: normal;">_T365X200</b> = Thermal Tab size is 3.65 mmX 2.00 mm rectangular <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>Using this technique will eliminate duplicate footprintnames with various Thermal Tab sizes. <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>There are also variances in the Lead Tolerance that willproduce a different footprint pattern pad size and spacing with the samefootprint name. <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 10pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>There is no guidance from IPC at this time on how tohandle variations in Lead Tolerances sizes. One of the recommendations PCBLibraries, Inc. has for various Lead sizes is to append the end of thefootprint name with underscore _ and “L” (for Lead) and the component LeadSize. <o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>Examples:<o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>SOP65P490X110-8rename to<o:p></o:p></span></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><span style='line-height: 115%; font-family: "Tahoma","sans-serif"; font-size: 10pt;'>SOP65P490X110-8<b style="mso-bidi-font-weight: normal;">_L38X68</b> = Lead size is 0.38 mm minimumand 0.68 mm maximum</p><div></div><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><o:p></o:p></span></p><font size="3" face="Times New Roman"></font></div>]]>
   </description>
   <pubDate>Tue, 22 Jan 2013 11:32:58 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2919.html#2919</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers : Hi Maarten,I did a batch output...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2918.html#2918</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=53">jameshead</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 22 Jan 2013 at 10:04am<br /><br />Hi Maarten,<br><br>I did a batch output of every footprint in the supplied-to-customers FPE.FPX file yesterday, with just the bog standard nominal output.<br><br>The resulting PADS .asc library took a while to import in to Pulsonix.&nbsp; It took half an hour for the progress bar to get up to about 15% so I let it run overnight.&nbsp; This morning I have a Pulsonix library with 3077 footprints in it (duplicated footprint names are not output by PCB FPX).<br><br>I ran a library report I created some time ago that lists footprints in a library together their pad styles.&nbsp; During the import Pulsonix found any duplicates in the technology file that you can download from PCB libraries and created new ones with sequential names.<br><br>In total there were:<br><br>114 new oval pad styles<br>903 new rectangle pad styles<br>32 new round pad styles<br>5 new rounded-rectangle pad styles<br>118 new square pad styles<br><br>That's 1172 new pad styles, and that's only for Nominal.&nbsp; There'd probably be about the same amount for Least and Maximum as well.<br><br>I certainly would have have the time to add all of these pad styles to a common technology file very quickly.<br><br>I am happy to give you a copy of the format file for the report if it's of interest to you, and the spreadsheet of results it came up with.<br><br>I wonder if it's worth getting Pulsonix users to collaborate on this?&nbsp; I wonder if it's worth the time?<br>]]>
   </description>
   <pubDate>Tue, 22 Jan 2013 10:04:30 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2918.html#2918</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers : &amp;#034;would it be possible that...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2913.html#2913</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=53">jameshead</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 21 Jan 2013 at 8:54am<br /><br />"would it be possible that the FPX export/Pulsonix import create the complete IPC pad name: like r100_200 and not just Rectangle1, 2, 3?"<br><br>Maarten, please excuse me if you know this already,<br><br>If you download the file "PulsonixPTF.zip that's linked at the top of the page:<br><br>http://www.pcblibraries.com/products/fpx/userguide/default.asp?ch=201<br><br>you will find a technology file in it called PCBFOOTPRINTEXPERT IMPORT.ptf that contains many IPC-7x51 named pad styles, as well as a mapping file for PADS ascii import to Pulsonix if you want to use it.<br><br>When you import your PADS ascii footprint into Pulsonix and use this technology file then if the pad style in the footprint already exists in the technology file then Pulsonix will automatically use it.<br><br>If the pad style is new then Pulsonix will substitute rectangle1 etc.<br><br>If you don't want to use this technology file but have one of your own then you can still import the pad styles in it to your own technology file by opening your technology file and selecting from the menu Setup then Technology then clicking the Load Technology button and selecting only Pad Styles in the list, then selecting the technology file PCBFOOTPRINTEXPERT IMPORT.ptf<br><br>I recommend that you have a technology file you use for importing and editing footprints all the time, and when you edit a footprint and rename a pad style to IPC-7x51 style, Pulsonix will prompt you saying the technology file has changed and ask if you want to save it.&nbsp; If you save it then each time you'll build up a collection of named IPC-7x51 pad styles that Pulsonix will automatically substitue if it finds a match.<br><br>It will work with pad styles using "By Layer" as well but I don't use this for my normal SMT pad styles - sorry.<br><br>I apologise if you know all this already.<br><br>If I had the time I would go through the customer FPX file and import them all to a blank library in Pulsonix and then go through and add every pad style as a named IPC-7x51 one to a single technology file and give to PCB Libraries but I regret I haven't got the time to do that at the moment, sorry.<br>]]>
   </description>
   <pubDate>Mon, 21 Jan 2013 08:54:05 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2913.html#2913</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers : Hi James &amp;amp; Tom,&amp;gt;&amp;gt;Do...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2912.html#2912</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=527">Maarten Verhage</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 21 Jan 2013 at 8:39am<br /><br />Hi James &amp; Tom,<br><br>&gt;&gt;<br>Do you specify different sizes for all your solder mask and solder paste layers using the "By Layer" in the Pad Style Technology setup?<br>&lt;&lt;<br><br>Yeah I do, then I can have rounded corners on the solder paste layer. No adjustments need to be done by the stencil people.<br><br>Tom, would it be possible that the FPX export/Pulsonix import create the complete IPC pad name: like r100_200 and not just Rectangle1, 2, 3?<br><br>Best regards,<br>Maarten<br><br>]]>
   </description>
   <pubDate>Mon, 21 Jan 2013 08:39:10 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2912.html#2912</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers :   The full blown very elaborate...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2911.html#2911</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 21 Jan 2013 at 8:01am<br /><br />The full blown very elaborate Padstack Editor (Manager) will be available in our V2013 when the "Package Editor" is released on March 1. <div>&nbsp;</div><div>Through-hole round, square and rectangular leads with round, square and oblong pad shape. Slotted holes. Plated, non-plated, keep-outs, pin name, pin coordinate and many other features are under development. We want everyone to build every part in the industry, not just the Standard parts.</div><div>&nbsp;</div><div>It's coming soon. </div><div>&nbsp;</div><div>BTW: V3013 will be released on February 1 (in two weeks) but the "Package Editor" won't be released until March 1. And 3D-STEP model export on March 1 too. </div><div>&nbsp;</div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Mon, 21 Jan 2013 08:01:18 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2911.html#2911</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers : Hi Maarten,Out of interest:Do...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2910.html#2910</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=53">jameshead</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 21 Jan 2013 at 7:58am<br /><br />Hi Maarten,<br><br>Out of interest:<br><br>Do you specify different sizes for all your solder mask and solder paste layers using the "By Layer" in the Pad Style Technology setup?<br><br>I use a global setting in the Layer class to increase solder mask or decrease solder paste by a set amount.&nbsp; On thermals though I use the "by layer" to turn off solder paste on pads where FPX has brought in a drawn polygon for solder paste apertures - such as a window design.<br>]]>
   </description>
   <pubDate>Mon, 21 Jan 2013 07:58:11 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2910.html#2910</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers : Hi Tom,I see, but how about completing...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2909.html#2909</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=527">Maarten Verhage</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 21 Jan 2013 at 7:39am<br /><br />Hi Tom,<br><br>I see, but how about completing the padstack manager. When can we have full control over the solder mask, paste mask and possibly user defined layers? Ideally I would like to import these into Pulsonix having solder mask and paste mask layers in the pads.<br><br>Best regards,<br>Maarten Verhage<br>]]>
   </description>
   <pubDate>Mon, 21 Jan 2013 07:39:21 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2909.html#2909</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers :      The first module for...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2602.html#2602</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 06 Dec 2012 at 1:35pm<br /><br /><p>The first module for the FPE was to recreate what we already done for IPC-7351 for “<strong>Standard</strong>” component families. The component dimensions and attribute data are stored in a FPX file. This technology is available right now. </p><div>&nbsp; </div><div>The second module for FPE is for non-standard through-hole and surface mount&nbsp;packages called “<strong>Footprint Designer</strong>”. This will allow the user to interactively insert holes and define component outlines. The user has complete control of the hole-size, plate or no plate, pin numbering and hole-placement by snap grid or coordinates. The package data will be stored in a PKG file. The user defines preferences for padstacks and outlines and applies their preferences to the holes and outline to auto-generate the footprint. The “Package Editor” will be able to create any through-hole connector or electronic package. The Package Editor will be ready for release in March 2013 and will sell as an add-on module to FPE. </div><div>&nbsp;</div><div><strong>Parts on Demand</strong> (POD) will be a web based PCB library vending machine that will sell FPX, PKG and FPT files for $1 each. The POD website will contain over 400,000 component package dimensional data mapped to 30 million component manufacturer logical part numbers and logical descriptions. Members of the electronics industry will upload FPX, PKG and FPT files in exchange for credits to download as many parts as they upload (or pay $1 per part). Every component package will be identified with contact information of who contributed it. Every part will have a 5-star rating system with comments. Poorly rated parts will be fixed immediately or removed from the site. Unrated parts will have a non-disclosure and the first company to download an unrated part must quality control the data and rates the part. The POD website <a href="http://www.pcbpod.com" target="_blank" rel="nofollow">www.pcbpod.com</a> is expected to go on-line in March or April 2013, but it will take a couple years to fully upload every component package in the electronics industry. We imagine that the POD project will never be fully completed and will expand as component manufacturer’s produce new package data. </div><div>Library files that will be available will include - Schematic Symbols, 3D Models, FPX files and&nbsp;mfr. recommended footprints in every CAD tool format (prebuilt parts). </div><div>&nbsp;&nbsp;</div><div>We will have to add more features to FPE to customize the program for each CAD tool. Example: The Allegro interface will need special features that are unique to Cadence tools.</div><div>&nbsp;</div><p>&nbsp;</p>]]>
   </description>
   <pubDate>Thu, 06 Dec 2012 13:35:30 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2602.html#2602</guid>
  </item> 
  <item>
   <title><![CDATA[SMT Headers : Has there been any thought given...]]></title>
   <link>https://www.PCBLibraries.com/forum/smt-headers_topic736_post2601.html#2601</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1067">chads108</a><br /><strong>Subject:</strong> 736<br /><strong>Posted:</strong> 06 Dec 2012 at 1:00pm<br /><br />Has there been any thought given to putting some type of calculator for SMT Headers/Connectors in the tool?<br><br>Chad<br>]]>
   </description>
   <pubDate>Thu, 06 Dec 2012 13:00:15 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/smt-headers_topic736_post2601.html#2601</guid>
  </item> 
 </channel>
</rss>