PCB Libraries Forum : 1008 Chip Inductor Land Pattern https://www.PCBLibraries.com/forum/ Tue, 07 Apr 2026 17:15:11 +0000 Fri, 26 Mar 2021 11:41:47 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 360 https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=2858 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[1008 Chip Inductor Land Pattern : Hello Tom,thanks for the insightful...]]> https://www.PCBLibraries.com/forum/1008-chip-inductor-land-pattern_topic2858_post11378.html#11378 Author: Lukas
Subject: 2858
Posted: 26 Mar 2021 at 11:41am

Hello Tom,

thanks for the insightful and prompt reply. I'll use the IPC-based land patterns for the murata inductors.

Best Regards

Lukas
]]> Fri, 26 Mar 2021 11:41:47 +0000 https://www.PCBLibraries.com/forum/1008-chip-inductor-land-pattern_topic2858_post11378.html#11378 <![CDATA[1008 Chip Inductor Land Pattern : The only consideration for a pad...]]> https://www.PCBLibraries.com/forum/1008-chip-inductor-land-pattern_topic2858_post11377.html#11377 Author: Tom H
Subject: 2858
Posted: 25 Mar 2021 at 5:54pm

The only consideration for a pad stack width to be smaller than the Terminal Lead is the Wave Solder process for bottom side mounted SMD packages. 

The IPC-7351 mathematical model includes the Terminal Lead Width and the Width Tolerance. This will always result in a pad size greater than the Terminal Width. 

However, this can be controlled by editing the solder joint "side" goals by making it a negative value. 

]]> Thu, 25 Mar 2021 17:54:04 +0000 https://www.PCBLibraries.com/forum/1008-chip-inductor-land-pattern_topic2858_post11377.html#11377 <![CDATA[1008 Chip Inductor Land Pattern : Hello There,in their specifications...]]> https://www.PCBLibraries.com/forum/1008-chip-inductor-land-pattern_topic2858_post11376.html#11376 Author: Lukas
Subject: 2858
Posted: 25 Mar 2021 at 5:25pm

Hello There,

in their specifications https://www.murata.com/~/media/webrenewal/support/library/catalog/products/inductor/chip/o05e.ashx page 130 (LQM2HP_EH), murata recommends a pad width (c) of 1.5mm which is considerably less than the width of the package/metalisation of 2.0mm. I tried to find any explanation for this, as I've never seen pads smaller than the width of the package.

For capacitors, murata also recommends making the pad smaller than the width, mentioning that this reduces stress: https://www.murata.com/en-us/support/faqs/products/capacitor/ceramiccapacitor/mnt/0008

Other manufacturers of similar-sized inductors propose more reasonable looking footprints: https://media.digikey.com/pdf/Data%20Sheets/Samsung%20PDFs/CIGT252010EH2R2MNE_Spec.pdf

Are there any IPC recommendations that would call for reduced pad widths as suggested by Murata?

Best Regards

Lukas
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