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  <title>PCB Libraries Forum : Yellow Warning Dot</title>
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  <pubDate>Tue, 07 Apr 2026 20:49:07 +0000</pubDate>
  <lastBuildDate>Wed, 24 Oct 2012 14:17:09 +0000</lastBuildDate>
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   <title><![CDATA[Yellow Warning Dot :   If you look at the &amp;#039;Calculation&amp;#039;...]]></title>
   <link>https://www.PCBLibraries.com/forum/yellow-warning-dot_topic249_post2124.html#2124</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=201">Jeff.M</a><br /><strong>Subject:</strong> 249<br /><strong>Posted:</strong> 24 Oct 2012 at 2:17pm<br /><br />If you look at the 'Calculation' Tab under the 'Footprint' tab&nbsp;you'll see a 'Footprint' Groupbox.<div>This will have statistics for all pad dimensions including the 'goal', 'minimum' as 'maximum' protrusions.</div><div>Normally the 'minimum' will be very close or equal to the 'goal' (depending on how your roundoffs are set).</div><div>The 'minimum' deviation from the 'goal'&nbsp;will reflect&nbsp;how much any dimension&nbsp;was trimmed.</div>]]>
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   <pubDate>Wed, 24 Oct 2012 14:17:09 +0000</pubDate>
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   <title><![CDATA[Yellow Warning Dot :   The PCB Footprint Program...]]></title>
   <link>https://www.PCBLibraries.com/forum/yellow-warning-dot_topic249_post2066.html#2066</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 249<br /><strong>Posted:</strong> 21 Oct 2012 at 3:01pm<br /><br />The PCB Footprint Program auto-trims pad side to side when the pad to pad rule in preferences is violated. <div>&nbsp;</div><div>How much pad is trimmed is&nbsp;difficult to list in the "Warning" box.&nbsp;Simply&nbsp;make&nbsp;the component lead width maximum tolerance a smaller number until the error message goes away. </div><div>&nbsp;</div><div>You can also adust the minimum pad to pad clearance value to a smaller number to see if the error message disappears. </div><div>&nbsp;</div><div>It is very rare when the program Trims Pads to meet the design rule of 6 mil pad to pad spacing. </div><div>&nbsp;</div><div>&nbsp;</div>]]>
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   <pubDate>Sun, 21 Oct 2012 15:01:55 +0000</pubDate>
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   <title><![CDATA[Yellow Warning Dot :  Select Dual Flat No-lead (DFN...]]></title>
   <link>https://www.PCBLibraries.com/forum/yellow-warning-dot_topic249_post604.html#604</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=10">RLS2004</a><br /><strong>Subject:</strong> 249<br /><strong>Posted:</strong> 29 May 2012 at 5:30pm<br /><br />Select Dual Flat No-lead (DFN 4 Pins). OK. Reference. OK.<br>&nbsp;<br>At this point there is a yellow dot in the component display window. This indicates an error or warning. Could the offended rule be highlighted in yellow? <br>&nbsp;<br>I see in Calculation the "Side Dimension trimmed to maintain clearance" ... Knowing "<strong>How much was it trimmed</strong>"&nbsp; as well as the offended rule, would be a welcome addition.<div>&nbsp;</div>]]>
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   <pubDate>Tue, 29 May 2012 17:30:10 +0000</pubDate>
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