PCB Libraries Forum https://www.PCBLibraries.com/forum/ Fri, 03 Apr 2026 20:49:45 +0000 Mon, 23 Mar 2026 08:46:09 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 30 https://www.PCBLibraries.com/forum/RSS_topic_feed.asp <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[Questions & Answers : How To Choose the Footprint for SMD Chip Resistor]]> https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14492.html#14492 Author: Tom H
Subject: How To Choose the Footprint for SMD Chip Resistor
Posted: 23 Mar 2026 at 8:46am

Here is the original EIA PDP-100 Chip Package dimensions and tolerances. 

https://www.pcblibraries.com/Forum/chips_topic3598.html

Compare with IEC.

]]> Mon, 23 Mar 2026 08:46:09 +0000 https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14492.html#14492 <![CDATA[Questions & Answers : How To Choose the Footprint for SMD Chip Resistor]]> https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14491.html#14491 Author: Ariel_Levy
Subject: How To Choose the Footprint for SMD Chip Resistor
Posted: 23 Mar 2026 at 12:58am

Tom thank you very much Smile
and thank you Feynman

My difficulty is in obtaining information the thickness of the contacts size of the component (the size "T")
I bought the IPC-7351 and 7352. and you don't have information about this.
I think to buy EIA-JEP95 , and don't know it's worth the money if very MFG design is contacts size what "he" want's.

This table i found is accurate?


How you handle this with general discrete components ,when the contacts size can be between 0.10 to 0.40?
With the IPC-7351 when contacts size is 0.4 mm?
]]> Mon, 23 Mar 2026 00:58:01 +0000 https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14491.html#14491 <![CDATA[Questions & Answers : How To Choose the Footprint for SMD Chip Resistor]]> https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14490.html#14490 Author: feynman
Subject: How To Choose the Footprint for SMD Chip Resistor
Posted: 22 Mar 2026 at 10:14am

Ask a/your assembler. They probably assembled millions of parts and are probably the best source for a reliable footprint.]]> Sun, 22 Mar 2026 10:14:58 +0000 https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14490.html#14490 <![CDATA[Questions & Answers : How To Choose the Footprint for SMD Chip Resistor]]> https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14489.html#14489 Author: Tom H
Subject: How To Choose the Footprint for SMD Chip Resistor
Posted: 22 Mar 2026 at 8:14am

IPC-7351 uses Min/Max Mode technology. the resulting footprint takes into consideration the package tolerances to calculate the pad stacks. The solder pattern should accommodate the package in the minimum, nominal and maximum material condition. 

The average 0402 tolerance range is +/-0.05 to +/-0.10. 

It seems like component manufacturers use their nominal package dimensions and add a Toe, Heel and Side. They use Nominal Mode technology and ignore the tolerances they provide in their datasheets. 

The average dimensions on an 0402 are L=1.00, W=0.50, T=0.25. 

Your pad stack pattern will depend on what dimensions and tolerances you use. 

However, if you run into a 0402 chip manufacturer that has tolerances greater than 0.10, I would highly question the accuracy of their machine process. 

Ideally, manufacturers try to produce packages that are Nominal Material Condition. That's the goal. Maybe in the future package tolerances will be 0.00 and then the Nominal Mode technology will take over and the IPC-7351 mathematical model will be history. 

]]> Sun, 22 Mar 2026 08:14:56 +0000 https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14489.html#14489 <![CDATA[Questions & Answers : How To Choose the Footprint for SMD Chip Resistor]]> https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14488.html#14488 Author: Ariel_Levy
Subject: How To Choose the Footprint for SMD Chip Resistor
Posted: 22 Mar 2026 at 5:07am

How do you choosethe footprint for SMD Resistor case 0402?

Vishay have3 recommendations for footprints.

Yageo onerecommended but it’s different from Vishay.

Vishay recommendation:

L=0.50 A=0.40 B=0.60

BASED ONIPC-7351

L=0.40 A=0.55B=0.60

BASED ON IEC 61188-6-2

L=0.55 A=0.35B=0.55

Yageo

L=0.50 A=0.50 B=0.60

 

I am very confused by all the recommendations.

I would appreciate a suggestion or any guidance on how to choose a footprint.


]]> Sun, 22 Mar 2026 05:07:04 +0000 https://www.PCBLibraries.com/forum/how-to-choose-the-footprint-for-smd-chip-resistor_topic3630_post14488.html#14488 <![CDATA[Standard Components : Footprint Origin Crosshair and Target Scaling]]> https://www.PCBLibraries.com/forum/footprint-origin-crosshair-and-target-scaling_topic3629_post14487.html#14487 Author: Tom H
Subject: Footprint Origin Crosshair and Target Scaling
Posted: 18 Mar 2026 at 11:21am

Origin elements generally includea Crosshair and a Target (Circle). 

The elements scale themselves tothe part size within user definitions, in combination with hard-coded minimumand maximum limits.  Origin controls maybe found in the Drafting Options to include origin elements consist ofCrosshair, Target, both or neither.


The length of the crosshair linesare limited to a minimum of the smaller of, one half the minimum of thecourtyard length or width and not to exceed the Crosshair Sizeoption.  The displayed line length will be the specified linelength plus the line width.


 The target is scaled to maintain aconstant size relative to the crosshair and not exceed the Target Diametersize option.  The displayed target outside diameter will be thespecified size plus the line width.

The limits are to ensure theorigin always remains inside the footprint extents without becoming excessivelylarge or small. 


]]> Wed, 18 Mar 2026 11:21:28 +0000 https://www.PCBLibraries.com/forum/footprint-origin-crosshair-and-target-scaling_topic3629_post14487.html#14487 <![CDATA[Altium : Issue Creating New Footprint in Altium Workspace]]> https://www.PCBLibraries.com/forum/issue-creating-new-footprint-in-altium-workspace_topic3628_post14486.html#14486 Author: cioma
Subject: Issue Creating New Footprint in Altium Workspace
Posted: 17 Mar 2026 at 12:14pm

We have the same problem, I'd say this is an issue with Altium Designer, please raise a bug on their system an repost here.

Our workaround is importing PCBL footprint (running a script) into a local PCBLib library, making a copy of "template" footprint in A365 workspace and then manually selecting and copying all the footprint data from local PCBLib to A365 workspace footprint and then committing it. Don't forget to copy footprint name, description and height as well.
]]> Tue, 17 Mar 2026 12:14:33 +0000 https://www.PCBLibraries.com/forum/issue-creating-new-footprint-in-altium-workspace_topic3628_post14486.html#14486 <![CDATA[Altium : Issue Creating New Footprint in Altium Workspace]]> https://www.PCBLibraries.com/forum/issue-creating-new-footprint-in-altium-workspace_topic3628_post14485.html#14485 Author: laurence.donkers
Subject: Issue Creating New Footprint in Altium Workspace
Posted: 17 Mar 2026 at 4:45am

Hi everyone, 

I'm having an issue when using the Footprint Expert import scripts on a newly created footprint in my company's Altium365 Workspace.

My current workflow is this:
  1. In the Altium Explorer panel, I navigate to our Footprint models folder and click
    "(+) Add Footprint..."
  2. This creates a new item ID (PCC-###) and opens up a new Footprint libary file based on our workspace's footprint template
  3. I run the script generated by FPE by using File > Run Script... > From File etc.
  4. The footprint is generated properly within the new Footprint library file, but when I open the PCB Library panel, the script-generated footprint is added as a separate footprint within the file.
  5. If I try to "Save to server", I get a warning that two footprints are included in the file (since Altium workspace is set up to operate with max. one footprint per file)
  6. Since this is a workspace footprint library file, Altium actually grays out the "Add" and "Delete" buttons in the PCB Library panel, so it can't be manually deleted.
  7. If I choose to release as a single footprint, it actually deletes the script-generated footprint and keeps the template!
  8. I can work around this by then opening the newly released footprint library file and repeating the generation from script and then I can save it. However this is really not ideal, since the process has to be repeated.

Could the generated scripts be modified so that if it detects a workspace footprint file it replaces the currently open footprint, rather than creating a new one within the same file? 
]]> Tue, 17 Mar 2026 04:45:44 +0000 https://www.PCBLibraries.com/forum/issue-creating-new-footprint-in-altium-workspace_topic3628_post14485.html#14485 <![CDATA[Questions & Answers : Chip Caps and Resistor w/No Terminal Tolerance]]> https://www.PCBLibraries.com/forum/chip-caps-and-resistor-w-no-terminal-tolerance_topic3627_post14482.html#14482 Author: Tom H
Subject: Chip Caps and Resistor w/No Terminal Tolerance
Posted: 11 Mar 2026 at 8:31am

When L and L1 dimensions are the same, only enter L (don't enter duplicate dimensions). 

L1 is optional if it's different than L. 

I recommend that you open the free SM Discrete.fpx file and sort the Case Code Column. 

Then search for similar Case Codes from other manufacturers and see what their Terminal Lead Tolerances are. 

Sometimes the component manufacturer will only provide the Minimum dimension and you need to figure out the Maximum dimension. 

Average Terminal Tolerances for chip components by Case Code:
  • 01005 - 0.03
  • 0201 - 0.05
  • 0402 - 0.10
  • 0603 - 0.15
  • 0805 - 0.20
  • 1206 - 0.25
  • 1812 - 0.30

]]> Wed, 11 Mar 2026 08:31:10 +0000 https://www.PCBLibraries.com/forum/chip-caps-and-resistor-w-no-terminal-tolerance_topic3627_post14482.html#14482 <![CDATA[Questions & Answers : Chip Caps and Resistor w/No Terminal Tolerance]]> https://www.PCBLibraries.com/forum/chip-caps-and-resistor-w-no-terminal-tolerance_topic3627_post14480.html#14480 Author: pcbfreedomcad
Subject: Chip Caps and Resistor w/No Terminal Tolerance
Posted: 11 Mar 2026 at 5:14am

What is entered in the tool for L and L1, when there is no tolerance for lead length given in the datasheet? 

I am thinking of Chip Capacitor and Resistor terminal tolerances. 

]]> Wed, 11 Mar 2026 05:14:19 +0000 https://www.PCBLibraries.com/forum/chip-caps-and-resistor-w-no-terminal-tolerance_topic3627_post14480.html#14480