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  <pubDate>Tue, 19 May 2026 04:42:12 +0000</pubDate>
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   <title><![CDATA[General Discussion : IPC-7352 incorrect table content?]]></title>
   <link>https://www.PCBLibraries.com/forum/ipc7352-incorrect-table-content_topic3645_post14537.html#14537</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=19437">eCADLER_94</a><br /><strong>Subject:</strong> IPC-7352 incorrect table content?<br /><strong>Posted:</strong> 19 May 2026 at 3:48am<br /><br /><div>Hello, <br>I believe that table 3-6 "Leadless Components with Concave/Castellated Termination" cannot be correct. Let's take the Nominal column, here the Toe would be 0.15mm and the Heel 0.45mm. <br>In my opinion, it doesn't make much sense to pull the pad that far back. Also confusing is the note "to find Z dim" next to the Heel(JH). The formula for Z (overall length of land pattern) is: <br>Z = Lmax +2xJt <br>This therefore has nothing to do with the Heel.</div><div>In my opinion, the table values of Toe and Heel are swapped.<br>Do you see it that way too?"<br><br><img src="" border="0" /><br><br>Best regards<br>Johannes</div>]]>
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   <pubDate>Tue, 19 May 2026 03:48:35 +0000</pubDate>
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   <title><![CDATA[Version History : Footprint Expert 26.05 Released!!]]></title>
   <link>https://www.PCBLibraries.com/forum/footprint-expert-26-05-released_topic3644_post14535.html#14535</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1">Nick B</a><br /><strong>Subject:</strong> Footprint Expert 26.05 Released!!<br /><strong>Posted:</strong> 17 May 2026 at 11:16pm<br /><br /><a href="http://www.pcblibraries.com/downloads" target="_blank" rel="nofollow"><font color="#0066cc"><u>Version 26.05 was just released</u></font></a>!!<p dir="ltr" style="margin-right: 0px;"><img src="https://www.pcblibraries.com/Forum/uploads/1/PCBLDVDDownloadNow26.png" height="275" width="204" border="0" /></p><div><p ="ms&#111;normal"=""><b><u>Fixes &amp; Enhancements:</u></b></p><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">FP Designer:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Removed through-hole pin terminal leads in the viewer display</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">When group moving pads on the component outline, the silkscreen wasn't trimming</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Options:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Terminals:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Inward L-Lead: updated the 'heel'&nbsp;solder joint goals to match the documentation</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Outward L-Lead: fine-tuned the Side solder joint goals</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">BGA updated the Courtyard Excess. The original settings were too robust.&nbsp;</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Thermal Pad:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Can't change the 'Minimum Pattern to Pad Edge Space'&nbsp;to 0.00</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Changed the paste mask maximum percentage from 99% to 100%</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Changing the pad shape for Pin 1 and selecting the 'Change all Pin 1 shape - Yes'&nbsp;did not work properly</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Calculators:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">CAPAE &amp; Crystal - update the dimensions to accommodate Min/Max to be the same value</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">SOT23 Form Factor - updated the dropdown and the official Footprint Naming Convention document</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">SOD - fixed an issue with SOD footprints not loading due to adding the non-polarized version&nbsp;</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Library Editor:&nbsp;</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Library Manager was showing the wrong row count in the task bar after adding a new blank row or rows</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Importing an fpx into another fpx file can sometimes throw an exception</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">CAD Tool Interfaces:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Pantheon - units in millimeters is not getting written to the output script file</li></ul></ul><div><br></div></div>]]>
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   <pubDate>Sun, 17 May 2026 23:16:08 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Collapsing vs: Non-Collapsing BGA Balls]]></title>
   <link>https://www.PCBLibraries.com/forum/collapsing-vs-noncollapsing-bga-balls_topic1868_post14531.html#14531</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Collapsing vs: Non-Collapsing BGA Balls<br /><strong>Posted:</strong> 12 May 2026 at 8:01am<br /><br />The Non-Collapsing BGA calculator is used on fine pitch parts when you can't fanout all the pins in the PCB layout and you're only fanout option is via-in-pad.&nbsp;<div><br></div><div>Non-Collapsing BGA pads are bigger then collapsing BGA pads to allow an annular ring for the drilling process.&nbsp;</div><div><br></div><div>Also, if you need to solder mask define the BGA pad to pass drop tests, the solder mask will help with the pad attachment to the prepreg. During drop tests, the ball to pad joint will withstand a drop test, but a non solder mask defined pad could rip away from the prepreg causing the device to malfunction.&nbsp;</div><div><br></div><div><br></div>]]>
   </description>
   <pubDate>Tue, 12 May 2026 08:01:54 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Collapsing vs: Non-Collapsing BGA Balls]]></title>
   <link>https://www.PCBLibraries.com/forum/collapsing-vs-noncollapsing-bga-balls_topic1868_post14530.html#14530</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=11979">m.elsayed</a><br /><strong>Subject:</strong> Collapsing vs: Non-Collapsing BGA Balls<br /><strong>Posted:</strong> 11 May 2026 at 8:29pm<br /><br />Is the information on collapsing or non collapsing be mentioned in supplier datasheets?<div><br></div><div>Or does it just depend on the pin pitch value only?</div><div><br></div><div>Also is the pitch value found in IPC-7352 standard?</div><div><br></div>]]>
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   <pubDate>Mon, 11 May 2026 20:29:25 +0000</pubDate>
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   <title><![CDATA[Product Suggestions : Adding Footprint Naming Convention Twice]]></title>
   <link>https://www.PCBLibraries.com/forum/adding-footprint-naming-convention-twice_topic3528_post14529.html#14529</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Adding Footprint Naming Convention Twice<br /><strong>Posted:</strong> 10 May 2026 at 2:18pm<br /><br />The PCB Libraries Naming Convention includes IPC-7352 for through-hole.&nbsp;<div><br></div><div>IPC-7351B naming convention for Surface Mount is very close to IPC-7352.&nbsp;</div><div><br></div><div>IPC-7352 naming convention for surface mount was enhanced to include Thermal Pad, Terminal Lead and BGA Ball Diameter data.&nbsp;</div><div><br></div><div>I would not use IPC-7351B for anything, including the mathematical model, solder joint goals, and naming conventions. 7351B is 16 years old and obsolete.&nbsp;</div><div><br></div>]]>
   </description>
   <pubDate>Sun, 10 May 2026 14:18:10 +0000</pubDate>
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   <title><![CDATA[Product Suggestions : Adding Footprint Naming Convention Twice]]></title>
   <link>https://www.PCBLibraries.com/forum/adding-footprint-naming-convention-twice_topic3528_post14528.html#14528</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=11979">m.elsayed</a><br /><strong>Subject:</strong> Adding Footprint Naming Convention Twice<br /><strong>Posted:</strong> 10 May 2026 at 8:35am<br /><br />When I check PCB Libraries Naming Convention, what IPC standard naming will be applied for through-hole parts?<div><div><span lang="EN-CA" style="font-size:10.0pt;font-family:  &quot;Arial&quot;,sans-serif;mso-fareast-font-family:&quot;Times New Roman&quot;;mso-bidi-font-family:  &quot;Times New Roman&quot;;:lime;mso-highlight:lime;mso-ansi-:EN-CA;  mso-fareast-:EN-US;mso-bidi-:AR-SA"><br></span></div></div>]]>
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   <pubDate>Sun, 10 May 2026 08:35:16 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : Trimming heels under the component body]]></title>
   <link>https://www.PCBLibraries.com/forum/trimming-heels-under-the-component-body_topic12_post14522.html#14522</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Trimming heels under the component body<br /><strong>Posted:</strong> 27 Apr 2026 at 8:32am<br /><br />The link is for a paper that I wrote when I was employed by Mentor Graphics in 2010.&nbsp;<div><br></div><div>Siemens took it down.&nbsp;</div><div><p ="xxms&#111;normal">Minimum Trim Standoff: <o:p></o:p></p><ul style="margin-top:0in" ="disc"> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Only affects Gullwing Leads the A1 dimension <o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Dieter Bergman said pad trimming is not an IPC-7351 Standard</span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">IPC J-STD-001 says that pads under low profile parts with A1     dimension is 0.00 should be trimmed for plastic body packages<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">The default setting is 0.03 meaning that any A1     dimension less than 0.03 will get trimmed<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">The trimming is to the Nominal Package Body dimension<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Many people turn it off by entering a value of 0.00<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Some people tone it down to 0.01 so that it only     affects part with A1 being 0.00<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">The main reason for customers who requested this     feature was to compensate for component manufacturers to limit their ‘L’     tolerance. In most 1.27 mm pitch SOICs, the ‘L’ dimension is min 0.41 and     max 1.27. The tolerance is +/-0.43. <o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Today, component manufacturers have a maximum ‘L’     tolerance of +/- 0.25 and a nominal tolerance of +/- 0.15. <o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">See the attached TI Case Code D0008A. the ‘L’ tolerance     is +/- 0.43 which is too robust so Texas Instruments Recommended Pattern     trims the pad from going under the package.</span></li></ul><p ="xxms&#111;normal">Summary: if the ‘L’ tolerance is +/- 0.15 there’s no needfor trimming. Even component manufacturers don’t use their ‘<b>L’ </b>tolerance fortheir pad stack calculation. A ‘<b>L</b>’ tolerance of 0.43 is way too robust, but inthe 1980s and 1990s the ‘<b>L</b>’ tolerance was +/- 0.43 but today it’s +/- 0.15. Thelarge ‘<b>L</b>’ tolerance is the only reason for Minimum Trim Standoff Height.</p><p ="xxms&#111;normal">I hope this explains the issue.</p><p ="xxms&#111;normal"><br></p><br></div>]]>
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   <pubDate>Mon, 27 Apr 2026 08:32:08 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : Trimming heels under the component body]]></title>
   <link>https://www.PCBLibraries.com/forum/trimming-heels-under-the-component-body_topic12_post14521.html#14521</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=11979">m.elsayed</a><br /><strong>Subject:</strong> Trimming heels under the component body<br /><strong>Posted:</strong> 27 Apr 2026 at 4:59am<br /><br />Thanks,&nbsp;<div><br></div><div>I have touched this point and try use the explanation here to understand point, however I notice the below link doesn't work.&nbsp;</div><div><br></div><div>Can provide working link please to check it's content.</div><div><br></div><div><a href="http://communities.mentor.com/mgcx/servlet/JiveServlet/download/28883-8838/PCB%20Design%20Optimizati&#111;n%20Starts%20in%20the%20CAD%20Library.pdf" target="_blank" rel="nofollow">http://communities.mentor.com/mgcx/servlet/JiveServlet/download/28883-8838/PCB%20Design%20Optimization%20Starts%20in%20the%20CAD%20Library.pdf</a><div><br></div></div>]]>
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   <pubDate>Mon, 27 Apr 2026 04:59:32 +0000</pubDate>
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   <title><![CDATA[General Discussion : Which PCB Design Software is the Best?]]></title>
   <link>https://www.PCBLibraries.com/forum/which-pcb-design-software-is-the-best_topic3020_post14519.html#14519</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=19515">Digitalmonk</a><br /><strong>Subject:</strong> Which PCB Design Software is the Best?<br /><strong>Posted:</strong> 22 Apr 2026 at 4:26am<br /><br />There is no single “best” PCB design software—it really depends on your project requirements and experience level.&nbsp;<div><br></div><div>For beginners, tools like <span =":entity-accent="" entity-underline="" inline="" cursor-pointer="" align-line"="">KiCad</span> are great because they are free and easy to use.&nbsp;</div><div><br></div><div>For advanced and complex designs, solutions like <span =":entity-accent="" entity-underline="" inline="" cursor-pointer="" align-line"="">Altium Designer</span> or <span =":entity-accent="" entity-underline="" inline="" cursor-pointer="" align-line"="">OrCAD</span> are more suitable.&nbsp;</div><div><br></div><div>Also, choosing the right tools is important when working on<a href="https://digitalm&#111;nk.biz/electr&#111;nics-&#101;mbedded-software-development-services/" target="_blank" rel="nofollow"> Embedded Software Development services</a>, as hardware and software integration plays a key role.</div><div><br></div>]]>
   </description>
   <pubDate>Wed, 22 Apr 2026 04:26:15 +0000</pubDate>
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   <title><![CDATA[Version History : Footprint Expert 26.04 Released!!]]></title>
   <link>https://www.PCBLibraries.com/forum/footprint-expert-26-04-released_topic3641_post14518.html#14518</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1">Nick B</a><br /><strong>Subject:</strong> Footprint Expert 26.04 Released!!<br /><strong>Posted:</strong> 21 Apr 2026 at 2:41pm<br /><br /><a href="http://www.pcblibraries.com/downloads" target="_blank" rel="nofollow"><font color="#0066cc"><u>Version 26.04 was just released</u></font></a>!!<p dir="ltr" style="margin-right: 0px;"><img src="https://www.pcblibraries.com/Forum/uploads/1/PCBLDVDDownloadNow26.png" height="275" width="204" border="0" /></p><div><p ="ms&#111;normal"=""><b><u>Fixes &amp; Enhancements:</u></b></p><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">FP Designer:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Creating a surface mount Bottom Side pad with solder mask, the Pad Stack Name did not include the solder mask</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">When selecting a Bottom Side SMD pad that was placed, the program opened the wrong properties dialog box</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Fixed an issue with courtyard excess for Bottom Side SMD pad stacks</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Added a new feature for adding lead zero's for A01 - A09</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Updated the ODA Pad Stack Naming Convention Documentation</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Fixed an issue with pan and zoom. When adding pins, sometimes the program locked up</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Library Editor:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">New feature for adding New Rows and Copy/Paste an existing row into the new rows without the Part Number</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">When all the cell data is the same except the part numbers are different</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Saving footprint rotation in FPX was removed. The footprint rotation now follows the Master Options.</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Cleaned up the user interface editing functions including Undo/Redo</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">When updating a Row, the program didn't ask to update the Physical Description</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">When columns were deleted and a new FPX file was imported with the same column header, the additional columns were not added</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Calculators:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Surface Mount:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">LCC - 2-Sided version:</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">The heel did not follow the solder joint goals in Options</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">The pin 1 polarity dot was missing</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Through-hole:&nbsp;</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">SIP - Single-Inline-Package:</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">No silkscreen trimming for offset pads</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Footprint Name wasn't getting the correct pin pitch&nbsp;</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">All component families can now move to FP Designer</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Options:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Through-hole Rounded Square pad shape did not follow the Option settings when assigned to the 'Default Pad Shape'</li></ul></ul><div><br></div><div><br></div></div>]]>
   </description>
   <pubDate>Tue, 21 Apr 2026 14:41:49 +0000</pubDate>
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