PCB Libraries Forum : QFN footprint trade-off - isolation or pad size ? https://www.PCBLibraries.com/forum/ Sat, 16 May 2026 01:05:45 +0000 Wed, 25 Jan 2023 01:03:58 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 360 https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=3214 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[QFN footprint trade-off - isolation or pad size ? : Hello,Thank you for the reply...]]> https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12791.html#12791 Author: sot23
Subject: 3214
Posted: 25 Jan 2023 at 1:03am

Hello,

Thank you for the reply !
Also, i saw your video on youtube with Fedevel Academy, very informative !! Thanks for your work.
]]> Wed, 25 Jan 2023 01:03:58 +0000 https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12791.html#12791 <![CDATA[QFN footprint trade-off - isolation or pad size ? : The reason why the component manufacturer...]]> https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12787.html#12787 Author: Tom H
Subject: 3214
Posted: 24 Jan 2023 at 10:40am

The reason why the component manufacturer recommended a 0.20 pad width is to help center the package on the pads. 

You cannot run a signal trace or copper pour between the pads. They're too close and would violate the design rules. 

I would say that any pad width between 0.20 and 0.25 is acceptable. 

]]> Tue, 24 Jan 2023 10:40:32 +0000 https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12787.html#12787 <![CDATA[QFN footprint trade-off - isolation or pad size ? : Hello and thank you for the answer....]]> https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12786.html#12786 Author: sot23
Subject: 3214
Posted: 24 Jan 2023 at 1:48am

Hello and thank you for the answer. The part is a TMS320 microcontroller, F280049RSHSR version. Datasheet available here : https://www.ti.com/product/TMS320F280049.

As you mention, it seems logical that the pad width should be equal or greater than the lead terminal width. But why does TI suggest to use 0.2mm pad when they also state that the terminal lead width range from 0.15mm to 0.25mm ?
]]> Tue, 24 Jan 2023 01:48:18 +0000 https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12786.html#12786 <![CDATA[QFN footprint trade-off - isolation or pad size ? : Can you please post what the TI...]]> https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12783.html#12783 Author: Tom H
Subject: 3214
Posted: 23 Jan 2023 at 8:32am

Can you please post what the TI Part Number is? 

The Case Code is RSH0056D, but we need the Part Number. 

The pad width should always be equal or greater than the terminal lead width. 

But you also have a minimum 0.15 gap between pads. 

]]> Mon, 23 Jan 2023 08:32:26 +0000 https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12783.html#12783 <![CDATA[QFN footprint trade-off - isolation or pad size ? : Hello,There is a question that...]]> https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12782.html#12782 Author: sot23
Subject: 3214
Posted: 23 Jan 2023 at 6:54am

Hello,

There is a question that I often have to ask myself when designing footprints for fine pitch QFN or SON package.

For exemple, here we have a VQFN package from TI : https://www.ti.com/lit/ml/qfnd364b/qfnd364b.pdf?keyMatch=RSH%252056&tisearch=Search-EN-everything (drawing : RSH0056D if the link doesn't work).
It has a pitch of 0.4mm. The pin size on the device is 0.15mm-0.25mm.

In order to be able to solder correctly the QFN to the board, I would have drawn padstacks with a width of 0.25mm to accomodate the biggest that the pin can get. But if I do that, I will have a pin to pin spacing of 0.15mm, and I see a lot of people recommending to not go under 0.2mm.

The only solution would be to create padstacks with a width of 0.2mm. It would allow the pin to pin spacing to be 0.2mm. But now the padstack is smaller that the biggest the pin can get...

What would you do in this situation? What is the worst, risking to bridge the padstacks with a pin to pin spacing that is to small ? Or risking to have bad contact with a padstack that is to small ? 
TI decided to avoid the bridging risk and recommend 0.2mm wide pads. My boss tell me 0.15 pin to pin spacing is just fine and to design a 0.25mm padstack...

More generally, how do you deal with this kind of tradeoffs ? What are the considerations to prioritize ? 

Thank you ! I wish you a great day !
]]> Mon, 23 Jan 2023 06:54:04 +0000 https://www.PCBLibraries.com/forum/qfn-footprint-tradeoff-isolation-or-pad-size_topic3214_post12782.html#12782