PCB Libraries Forum : VIA Guidance Request From Tim C.

VIA Guidance Request From Tim C. : Answer 1 - You must use blind...

Thu, 06 Sep 2012 12:38:53 +0000

Author: Tom H
Subject: 538
Posted: 06 Sep 2012 at 12:38pm

Answer 1 - You must use blind vias when a double sided assembly is too dense to use through-hole vias. One of the best tricks in the trade is to place all "Digital" parts on one side and all "Analog" parts on the other. The board is split in two. Place the AGND planes by the Analog parts and DGND planes by the Digital parts. The blind vias will connect to the correct layers. If the design requires that Analog and Digital signals need to share then those signals will require a through-hole via or a buried via.

Answer 2 - There are some good calculators here - http://www.ultracad.com/calc.htm and here - http://www.saturnpcb.com/pcb_toolkit.htm for calculating trace widths and via sizes for optimizing current capacity.

Via holes are typically plugged when using via-in-pad technology and this includes via-in-thermal pad for QFN's. Since plugging adds a fabrication process the bare board cost increases. So if you want to plug a via you might as well plug all of them because the is no difference in cost for one plugged via or a thousand plugged vias.

If you do not mention the plug fill material in your fabrication notes, LPI solder mask is the default. But if you have high current you should probably request Dupont Silver Epoxy. Silver is a conductor and will help carry high current. If the via hole size is less than 14 mil (0.35 mm) you can set the hole tolerance to +0.00 / -0.014 (hole size) to allow the fabrication shop to plate the hole closed. I've heard of this technique but have never seen it used. Plugging vias is the norm.

VIA Guidance Request From Tim C. : I found a brief titled"Proper...

Thu, 06 Sep 2012 12:22:10 +0000

Author: timcrouse
Subject: 538
Posted: 06 Sep 2012 at 12:22pm

I found a brief titled "Proper Metric Etiquette" from PCB Libraries

It list the VIA to Track selection and good VIA hole to Pad info too.

Actually it would be nice if the Optimal VIA Padstack information could be expanded to include wider traces, at the present it covers up to 0.15 mm traces.

Up to 1 mm traces would be a good chart to have on hand.

VIA Guidance Request From Tim C. : Can someone provide guidance...

Thu, 06 Sep 2012 11:44:29 +0000

Author: timcrouse
Subject: 538
Posted: 06 Sep 2012 at 11:44am

Can someone provide guidance on the following VIA questions?

1. Using VIAs to connect SM Device pads together when one device is on the top layer and the other is directly below on the bottom layer.

2. Does anyone have a chart that shows sound information showing the relationship between VIA and trace sizes, for expample if I am running a .2mm trace what is a recommended pad size and a recommended plated hole size, people seem to mention the ring should be twice the hole size, I do not see how that can have the same current carrying capbility as teh trace coonect to it. Seems more like the ring size should be twice the hole size so no mtter where the trace connect to the ring it has the same amount of copper as the trace.

And then there are things to consider like a plated hole vs a plugged hole, just seems like folks have been doing this long enough that there should be some good rules of thumb available.

Thanks in advance

Tim C.