<?xml version="1.0" encoding="utf-8" ?>
<?xml-stylesheet type="text/xsl" href="RSS_xslt_style.asp" version="1.0" ?>
<rss version="2.0" xmlns:WebWizForums="https://syndication.webwiz.net/rss_namespace/">
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  <title>PCB Libraries Forum : Odd Looking Footprint for Chip Array</title>
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  <pubDate>Mon, 06 Apr 2026 17:44:01 +0000</pubDate>
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   <title><![CDATA[Odd Looking Footprint for Chip Array :     To summarize, the significant...]]></title>
   <link>https://www.PCBLibraries.com/forum/odd-looking-footprint-for-chip-array_topic510_post1619.html#1619</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 510<br /><strong>Posted:</strong> 29 Aug 2012 at 8:23am<br /><br /><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><font size="3"><font face="Times New Roman">To summarize, the significant differences are:<?: prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></font></font></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt 0.5in; text-indent: -0.25in; mso-list: l0 level1 lfo1;" ="MsoListParagraph"><span style="mso-fareast-font-family: Calibri;"><span style="mso-list: Ignore;"><font size="3" face="Calibri">1.</font><span style='font: 7ptormal "Times New Roman"; font-size-adjust: n&#111;ne; font-stretch: normal;'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span></span><font face="Calibri"><font size="3">Inthe Toe Goal…the manufacturer is ignoring the IPC toe</font></font></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt 0.5in; text-indent: -0.25in; mso-list: l0 level1 lfo1;" ="MsoListParagraph"><span style="mso-fareast-font-family: Calibri;"><span style="mso-list: Ignore;"><font size="3" face="Calibri">2.</font><span style='font: 7ptormal "Times New Roman"; font-size-adjust: n&#111;ne; font-stretch: normal;'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span></span><font face="Calibri"><font size="3">Inthe Heel Goal…the manufacturer is ignoring the IPC heel</font></font></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt 0.5in; text-indent: -0.25in; mso-list: l0 level1 lfo1;" ="MsoListParagraph"><span style="mso-fareast-font-family: Calibri;"><span style="mso-list: Ignore;"><font size="3" face="Calibri">3.</font><span style='font: 7ptormal "Times New Roman"; font-size-adjust: n&#111;ne; font-stretch: normal;'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span></span><font face="Calibri"><font size="3">LPWhas a smaller IPC toe than FPX (bug in LPW)</font></font></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt 0.5in; text-indent: -0.25in; mso-list: l0 level1 lfo1;" ="MsoListParagraph"><span style="mso-fareast-font-family: Calibri;"><span style="mso-list: Ignore;"><font size="3" face="Calibri">4.</font><span style='font: 7ptormal "Times New Roman"; font-size-adjust: n&#111;ne; font-stretch: normal;'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span></span><font face="Calibri"><font size="3">LPWhas different place and size rounds. 0.05 mm for LPW and 0.01 mm for FPX</font></font></p><font size="3" face="Times New Roman"></font><p style="margin: 0in 0in 0pt 0.5in; text-indent: -0.25in; mso-list: l0 level1 lfo1;" ="MsoListParagraph"><span style="mso-fareast-font-family: Calibri;"><span style="mso-list: Ignore;"><font size="3" face="Calibri">5.</font><span style='font: 7ptormal "Times New Roman"; font-size-adjust: n&#111;ne; font-stretch: normal;'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span></span><font size="3"><font face="Calibri">Finally,LPW has a minimum pad-to-pad spacing rule of 0.20 mm&nbsp;so it’s heel is being trimmedmore than FPX which has a minimum pad to pad of 0.15 mm.</p><div><o:p>&nbsp;</o:p></font></font></div><font size="3" face="Times New Roman"></font>]]>
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   <pubDate>Wed, 29 Aug 2012 08:23:32 +0000</pubDate>
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   <title><![CDATA[Odd Looking Footprint for Chip Array :   Sure, here&amp;#039;s a top-level...]]></title>
   <link>https://www.PCBLibraries.com/forum/odd-looking-footprint-for-chip-array_topic510_post1606.html#1606</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=246">LaserAlex</a><br /><strong>Subject:</strong> 510<br /><strong>Posted:</strong> 28 Aug 2012 at 1:48pm<br /><br />Sure, here's a top-level link:<div><a href="http://industrial.panas&#111;nic.com/www-cgi/jvcr13pz.cgi?E+PZ+3+AOC0001+EXB18V102JX+7+WW" target="_blank" rel="nofollow">http://industrial.panasonic.com/www-cgi/jvcr13pz.cgi?E+PZ+3+AOC0001+EXB18V102JX+7+WW</a></div><div>&nbsp;</div><div>The catalog with dimensions is here:</div><div><a href="http://industrial.panas&#111;nic.com/www-data/pdf/AOC0000/AOC0000CE1.pdf" target="_blank" rel="nofollow">http://industrial.panasonic.com/www-data/pdf/AOC0000/AOC0000CE1.pdf</a></div><div>and the recommended footprint is here:</div><div><a href="http://industrial.panas&#111;nic.com/www-data/pdf/AOC0000/AOC0000PE6.pdf" target="_blank" rel="nofollow">http://industrial.panasonic.com/www-data/pdf/AOC0000/AOC0000PE6.pdf</a></div><div>&nbsp;</div><div>If you look at the image in my first post, you'll see that Footprint Expert makes pads that are half as wide and twice as long as the recommended land pattern.&nbsp; The LP Wizard comes up with something pretty close to the manufacturer's recommendation.</div><div>&nbsp;</div>]]>
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   <pubDate>Tue, 28 Aug 2012 13:48:24 +0000</pubDate>
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   <title><![CDATA[Odd Looking Footprint for Chip Array :   Can you send us the datasheet...]]></title>
   <link>https://www.PCBLibraries.com/forum/odd-looking-footprint-for-chip-array_topic510_post1604.html#1604</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=201">Jeff.M</a><br /><strong>Subject:</strong> 510<br /><strong>Posted:</strong> 28 Aug 2012 at 12:48pm<br /><br />Can you send us the datasheet (or link)&nbsp;for the part you're creating so we can check it?]]>
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   <pubDate>Tue, 28 Aug 2012 12:48:43 +0000</pubDate>
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   <title><![CDATA[Odd Looking Footprint for Chip Array :   The PCB Footprint Expert is...]]></title>
   <link>https://www.PCBLibraries.com/forum/odd-looking-footprint-for-chip-array_topic510_post1603.html#1603</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 510<br /><strong>Posted:</strong> 28 Aug 2012 at 12:47pm<br /><br />The PCB Footprint Expert is a brand new tool that was written from scratch and during the process we discovered some mistakes we made with LP Wizard. <div>&nbsp;</div><div>Also, the new program uses a higher resolution of 0.01 mm snap grid round-off&nbsp;while LP Wizard uses a 0.05 mm round-off. </div><div>&nbsp;</div><div>If there are&nbsp;differences, they&nbsp;should only be 1 or 2 mils. </div><div>&nbsp;</div>]]>
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   <pubDate>Tue, 28 Aug 2012 12:47:23 +0000</pubDate>
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   <title><![CDATA[Odd Looking Footprint for Chip Array : Thanks, Tom.I&amp;#039;m OK with the...]]></title>
   <link>https://www.PCBLibraries.com/forum/odd-looking-footprint-for-chip-array_topic510_post1602.html#1602</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=246">LaserAlex</a><br /><strong>Subject:</strong> 510<br /><strong>Posted:</strong> 28 Aug 2012 at 12:41pm<br /><br />Thanks, Tom.<div><br></div><div>I'm OK with the general idea of entering the manufacturer's preferred footprint. &nbsp;However, it doesn't explain why PCB Footprint Expert gives a different recommended footprint than LP Wizard. &nbsp;If they are both using the same version of the IPC standard for their calculations, they should both produce identical land patterns. &nbsp;The fact that they don't seems like a possible bug to at least look in to.<br><br>In the mean time, I have created a footprint according to the manufacturer's instructions, I just want to make sure this doesn't cause a problem for any other users in the future.<div><br></div><div>Regards,</div><div><br></div><div>-Alex</div></div>]]>
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   <pubDate>Tue, 28 Aug 2012 12:41:23 +0000</pubDate>
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   <title><![CDATA[Odd Looking Footprint for Chip Array :   With 0201 microminiature components,...]]></title>
   <link>https://www.PCBLibraries.com/forum/odd-looking-footprint-for-chip-array_topic510_post1560.html#1560</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 510<br /><strong>Posted:</strong> 25 Aug 2012 at 8:51am<br /><br />With 0201 microminiature components, less solder is sometimes best and according to the IPC-7351 mathematical model that's true. <div>&nbsp;</div><div>However, if the component manufacturer did their due diligence and tested their recommended pattern and it passed all stress tests then I would consider using it. That is why we built into the new PCB Footprint Expert the ability to enter the component manufacturer recommended pattern dimensions. </div><div>&nbsp;</div><div>Every component family has a "Footprint" tab. After you insert all the component dimensions and select "OK" to calculate the IPC pattern, select the "Footprint" tab to compare the IPC pattern&nbsp;with the manufacturer's pattern dimensions. If they're way off, select the "Use Manufacturer's Recommended Dimensions" button and enter the pad length, width and separation dimensions and build that pattern. The IPC rules for Courtyard spacing will be auto-calculated and the silkscreen will be auto-trimmed to follow your silkscreen to pad rule. </div><div>&nbsp;</div><div><img src="uploads/3/Chip_Array_Footprint.png" height="700" width="811" border="0" /></div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Sat, 25 Aug 2012 08:51:33 +0000</pubDate>
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   <title><![CDATA[Odd Looking Footprint for Chip Array :  I was trying to create a footprint...]]></title>
   <link>https://www.PCBLibraries.com/forum/odd-looking-footprint-for-chip-array_topic510_post1559.html#1559</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=246">LaserAlex</a><br /><strong>Subject:</strong> 510<br /><strong>Posted:</strong> 25 Aug 2012 at 2:03am<br /><br />I was trying to create a footprint for a small (quad 0201) Panasonic chip array resistor. &nbsp;The footprint created by PCB Footprint Expert has really skinny lands, when compared to both the&nbsp;manufacturer's&nbsp;recommended footprints and the Mentor IPC footprint calculator I got with my copy of the IPC&nbsp;standard.<div><br></div><div>Is this a bug, or has the standard changed?</div><div><br></div><div>Thanks!</div><div><br></div><div><img src="uploads/246/ChipArray.jpg" border="0" /><br></div>]]>
   </description>
   <pubDate>Sat, 25 Aug 2012 02:03:36 +0000</pubDate>
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 </channel>
</rss>