<?xml version="1.0" encoding="utf-8" ?>
<?xml-stylesheet type="text/xsl" href="RSS_xslt_style.asp" version="1.0" ?>
<rss version="2.0" xmlns:WebWizForums="https://syndication.webwiz.net/rss_namespace/">
 <channel>
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  <docs>http://blogs.law.harvard.edu/tech/rss</docs>
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   <title><![CDATA[Transistor Outline (TO, DPAK) query :    The mfr. does not provide...]]></title>
   <link>https://www.PCBLibraries.com/forum/transistor-outline-to-dpak-query_topic474_post2119.html#2119</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 474<br /><strong>Posted:</strong> 23 Oct 2012 at 8:27pm<br /><br /> The mfr. does not provide the Maximum&nbsp;Thermal pad length (dimension "E2"). <div>&nbsp;</div><div>In that case, you should always Tweak the E2 dimension so that the Pad Length is at least equal to the mfr. recommended footprint (land pattern). </div><div>&nbsp;</div><div>The recommended footprint E2 dimension for one of the parts is - </div><div>6.99 mm&nbsp;- <a href="http://www.nati&#111;nal.com/packaging/mkt/ts5b.pdf" target="_blank" rel="nofollow">http://www.national.com/packaging/mkt/ts5b.pdf</a>&nbsp;</div><div>10.41 mm - <a href="http://www.ti.com/lit/ds/symlink/lm2595.pdf" target="_blank" rel="nofollow">http://www.ti.com/lit/ds/symlink/lm2595.pdf</a>&nbsp;</div><div>So there are 2 different footprint patterns (2 different FPX files). </div><div>&nbsp;</div><div>If you personally want to make a singe pattern that will fit both parts then you need to use the largest E2 value of the 2 components. You can also use the "Footprint" tab and enter the mfr recommended footprint values to create that unique pattern.</div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Tue, 23 Oct 2012 20:27:18 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/transistor-outline-to-dpak-query_topic474_post2119.html#2119</guid>
  </item> 
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   <title><![CDATA[Transistor Outline (TO, DPAK) query :  Could you confirm that this...]]></title>
   <link>https://www.PCBLibraries.com/forum/transistor-outline-to-dpak-query_topic474_post1410.html#1410</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=53">jameshead</a><br /><strong>Subject:</strong> 474<br /><strong>Posted:</strong> 24 Jul 2012 at 2:49am<br /><br />Could you confirm that this view and calculation is okay for National Semiconductor part LM2595S?<br><br>The datasheet is here:<br><br><a href="http://www.ti.com/lit/ds/symlink/lm2595.pdf" target="_blank" rel="nofollow">http://www.ti.com/lit/ds/symlink/lm2595.pdf</a> <br><br>But there's a better drawing here:<br><br><a href="http://www.nati&#111;nal.com/packaging/mkt/ts5b.pdf" target="_blank" rel="nofollow">http://www.national.com/packaging/mkt/ts5b.pdf</a> <br><br>Entered dimensions were:<br><br><img src="http://www.pcblibraries.com/forum/uploads/53/LM2595dimsentry.png" height="372" width="323" border="0" /><br><br>D1 and D were put in as the same value.<br><br>E Min was put in as 13.85 mm based on using a +/- 0.25 mm tolerance which I used based on the main tolerance they'd used of +/- 0.25 else where on the drawing - not too disimilar to the +/- 0.2 mm tolerance suggested by Tom earlier for missing dimensions.<br><br>I took L1 from the datasheet as 1.27 max and made a similar application of a +/- 0.25 mm tolerance, then worked out E1, E, and E2.<br><br>E1 max = 1.27 + (8.64 + 0.25) = 10.16 mm<br>E1 min = (1.27 - 0.5) + (8.64 - 0.25) = 9.16 mm<br><br>E2 max = 1.27 + (5.08 + 0.5) = 6.85 mm<br>E2 min = (1.27 - 0.5) + 5.08 = 5.85 mm<br><br>L was given as 1.98 with no tolerance so again I put in a +/- 0.25 mm tolerance.<br><br>L1 max = 1.27 mm<br>L1 min = 1.27 - 0.5 = 0.77 mm<br><br>Dimensions shown after entry were:<br><br><img src="http://www.pcblibraries.com/forum/uploads/53/LM2595dimscalculated.png" height="350" width="322" border="0" /><br><br>Footprint view is:<br><br><img src="uploads/53/LM2595footprintview.png" height="558" width="474" border="0" /><br><br><br>Normally I'd not be too bothered if I was just doing this footprint for myself but I am conciously aware that these may end up in FPX files used by others so just wanted some feedback on what's expected for these packages.<br><br><br><br>]]>
   </description>
   <pubDate>Tue, 24 Jul 2012 02:49:19 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/transistor-outline-to-dpak-query_topic474_post1410.html#1410</guid>
  </item> 
 </channel>
</rss>