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  <title>PCB Libraries Forum : PQFN/PSON Footprint Name</title>
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  <pubDate>Tue, 07 Apr 2026 03:09:39 +0000</pubDate>
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   <title><![CDATA[PQFN/PSON Footprint Name :  Thanks Tom,      Thank...]]></title>
   <link>https://www.PCBLibraries.com/forum/pqfn-pson-footprint-name_topic305_post2200.html#2200</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=412">rdl86626</a><br /><strong>Subject:</strong> 305<br /><strong>Posted:</strong> 29 Oct 2012 at 9:07am<br /><br /><font size="2" face="Verdana, Arial, Helvetica, sans-serif">Thanks Tom,</font><div>&nbsp;</div><div><font size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><font size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><font face="Verdana, Arial, Helvetica, sans-serif"><font size="2">&nbsp;&nbsp; Thank you very much and I see your point. Wehave boards that are ridgid flex with analog /digial mixed. I have 1 or 2traces that break that rule, which I do break if I have to, like you say commonsense is the best rule.</font></font></p><font size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><font face="Verdana, Arial, Helvetica, sans-serif"><font size="2">Thanks again.<?: prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></font></font></p><font size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><p style="margin: 0in 0in 0pt;" ="Ms&#111;normal"><font face="Verdana, Arial, Helvetica, sans-serif"><font size="2">not so dumb Rick<o:p></o:p></font></font></p><font size="2" face="Verdana, Arial, Helvetica, sans-serif"></font></div><div><font size="2" face="Verdana, Arial, Helvetica, sans-serif"></font>&nbsp;</div><div><font size="2" face="Verdana, Arial, Helvetica, sans-serif"></font>&nbsp;</div>]]>
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   <pubDate>Mon, 29 Oct 2012 09:07:07 +0000</pubDate>
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   <title><![CDATA[PQFN/PSON Footprint Name :  I don&amp;#039;t get all of the...]]></title>
   <link>https://www.PCBLibraries.com/forum/pqfn-pson-footprint-name_topic305_post2198.html#2198</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 305<br /><strong>Posted:</strong> 29 Oct 2012 at 8:55am<br /><br />I don't get all of the rules from IPC, but they do document a lot of DFM stuff in the IPC-2221 and IPC-2222. <div>&nbsp; </div><div>I use fabrication shops and common sense most of the time. </div><div>&nbsp; </div><div>Example: I went to Google and typed "DFM Guidelines" and I found this PDF file -</div><div><a href="http://irtfweb.ifa.hawaii.edu/~ao/Electr&#111;nic/Peter_dump/Electr&#111;nics/System/Text/PCBCADGuidelines.pdf" target="_blank" rel="nofollow">http://irtfweb.ifa.hawaii.edu/~ao/Electronic/Peter_dump/Electronics/System/Text/PCBCADGuidelines.pdf</a></div><div>&nbsp; </div><div>This document produced in Hawaii surveyed several California Fabrication shops - </div><ul><li>TTM</li><li>Velie Circuits</li><li>Multek</li><li>Dynamic Details</li><li>Via Systems</li><li>Fine Pitch</li></ul><p>There are comparisons between manufacturers. </p><div>You say to pull your planes back 40 mils but traces 20 mils. To me this means that you have traces without a reference plane below them. I wouldn't do that. </div><div>&nbsp;</div><div>The main reasons why features need to be pulled back from the board edge is the answer to your question. Is it because the fabrication shop is V-scoring or using a router. When breaking up the panel into individual boards, V-Scoreing can leave rough edges that need to be panelerized plus the process requires recessed features as not to damage them. </div><div>&nbsp;</div><div>Does your panel need to remain intact for assembly? If so, there will be breakaway rat-bite holes in the router process. </div><div>&nbsp;</div>]]>
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   <pubDate>Mon, 29 Oct 2012 08:55:49 +0000</pubDate>
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   <title><![CDATA[PQFN/PSON Footprint Name :   Tom,   I was reading the...]]></title>
   <link>https://www.PCBLibraries.com/forum/pqfn-pson-footprint-name_topic305_post2197.html#2197</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=412">rdl86626</a><br /><strong>Subject:</strong> 305<br /><strong>Posted:</strong> 29 Oct 2012 at 8:35am<br /><br /><p style="margin: 0in 0in 0pt;"><span style="color: navy; font-family: Arial; font-size: 10pt;"><font color="#000000" face="Verdana, Arial, Helvetica, sans-serif">Tom,</font></span></p><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><div><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><p style="margin: 0in 0in 0pt;"><?: prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p>&nbsp;</o:p></p><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><div><font color="#000000"><font face="Verdana, Arial, Helvetica, sans-serif"><span style="color: navy; font-family: Arial; font-size: 10pt;"><font color="#000000">I was reading the form where you stated</font> “</span><font size="2"><span style="color: black; font-family: Verdana; font-size: 7pt;"><font size="2"><strong>The minimum board edge to any feature - component, via, trace, copper pour is 40 mils (1.0 mm)”. </strong></font></span><span style="color: black; font-family: Arial; font-size: 10pt;">I</span><span style="color: black; font-family: Verdana; font-size: 7pt;"> </span><span style="color: black; font-family: Arial; font-size: 10pt;">have a hard time with IPC spec’s and where to find out things like that. </span></font></font></font></div><div><font color="#000000"><font face="Verdana, Arial, Helvetica, sans-serif"><font size="2"><span style="color: black; font-family: Arial; font-size: 10pt;">&nbsp;</span></font></font></font></div><div><font color="#000000"><font face="Verdana, Arial, Helvetica, sans-serif"><font size="2"><span style="color: black; font-family: Arial; font-size: 10pt;">I have been using .040 for planes and .020 for traces. What spec are these things in?</span></font></font></font></div><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><div><span style="color: black; font-family: Arial; font-size: 10pt;"></span><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif">&nbsp;</font></div><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><div><span style="color: black; font-family: Arial; font-size: 10pt;"><font color="#000000" face="Verdana, Arial, Helvetica, sans-serif">I don't mean to sound stupid, </font></span></div><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><div><span style="color: black; font-family: Arial; font-size: 10pt;"></span><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif">&nbsp;</font></div><font color="#000000" size="2" face="Verdana, Arial, Helvetica, sans-serif"></font><div><span style="color: black; font-family: Arial; font-size: 10pt;"><font color="#000000" face="Verdana, Arial, Helvetica, sans-serif">Dumb Rick</font></span></div><div><span style="color: black; font-family: Arial; font-size: 10pt;"><font face="Verdana">&nbsp;</font></span></div></div>]]>
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   <pubDate>Mon, 29 Oct 2012 08:35:59 +0000</pubDate>
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   <title><![CDATA[PQFN/PSON Footprint Name :   The minimum board edge to...]]></title>
   <link>https://www.PCBLibraries.com/forum/pqfn-pson-footprint-name_topic305_post2179.html#2179</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 305<br /><strong>Posted:</strong> 27 Oct 2012 at 8:02am<br /><br />The minimum board edge to any feature - component, via, trace, copper pour is 40 mils (1.0 mm). <div>&nbsp;</div><div>The minimum SMT component to component body or component pad to component pad gap is 10 mil (0.25 mm)&nbsp;for different components. </div><div>&nbsp;</div><div>The minumum pad to pad gap on the same component is 6 mils (0.15 mm). </div><div>&nbsp;</div><div>The minimum pad to thermal pad gap on the same component is 8 mils (0.20 mm). </div><div>&nbsp;</div><div>You can also get more information by reading my blog here - </div><div><a href="http://blogs.mentor.com/tom-hausherr/" target="_blank" rel="nofollow">http://blogs.mentor.com/tom-hausherr/</a>&nbsp;</div><div>&nbsp;</div><div>Copy/Paste the entire Blog into a Word document or print it out to PDF.&nbsp;We don't know how long Mentor Graphics&nbsp;will keep it available. </div><div>&nbsp;</div>]]>
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   <pubDate>Sat, 27 Oct 2012 08:02:39 +0000</pubDate>
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   <title><![CDATA[PQFN/PSON Footprint Name :    Hi,I am new user for this...]]></title>
   <link>https://www.PCBLibraries.com/forum/pqfn-pson-footprint-name_topic305_post2178.html#2178</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1201">Sanand</a><br /><strong>Subject:</strong> 305<br /><strong>Posted:</strong> 27 Oct 2012 at 2:01am<br /><br />Hi,<div>&nbsp;</div><div>I am new user for this site. I have some questions regarding the land pattern and wonder if this forum is suit for it. </div><div>&nbsp;</div><div>Do you know of any minimum clearance along the edge of&nbsp;PCB or memory module must be? Is it 0.050" to be minimum or 0.150"? </div><div>&nbsp;</div><div>And minimum gap between to components footprint or between two terminals of passive 0201?</div><div>&nbsp;</div><div>Thanks</div><div>&nbsp;</div>]]>
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   <pubDate>Sat, 27 Oct 2012 02:01:41 +0000</pubDate>
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   <title><![CDATA[PQFN/PSON Footprint Name :            The Component...]]></title>
   <link>https://www.PCBLibraries.com/forum/pqfn-pson-footprint-name_topic305_post2088.html#2088</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 305<br /><strong>Posted:</strong> 22 Oct 2012 at 10:39am<br /><br /><p align="left">The Component Lead Shape and the resulting Pad Shape have nothing to do with the footprint pattern name. </p><div>Here is a component manufacturer that produces QFN packages with D-shape Package Leads - </div><p align="left"><img src="uploads/3/QFN_Package_with_D-Shape_Leads.png" border="0" /><div align="center">&nbsp;</div><div>Here is their recommended footprint with Rectangular footprint pads. Also notice that the Component Thermal Tab has a Chamfer Corner by Pin 1 and rounded corners on the others, but the manufacturer recommends a solid square with no chamfer or rounded corners. So it's really a "User Option". </div><p align="left">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <img src="uploads/3/QFN_Recommended_Footprint.png" height="462" width="387" border="0" />&nbsp;<div>Also note that the manufacturer is calling the footprint a "Land Pattern" and they are using the IPC-7351 Land Pattern Naming Convention with the JEDEC variation in the Land Pattern Name (W6) to discriminate the Thermal Pad size. </div><div>&nbsp;</div>]]>
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   <pubDate>Mon, 22 Oct 2012 10:39:10 +0000</pubDate>
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   <title><![CDATA[PQFN/PSON Footprint Name : There are multiple instances with...]]></title>
   <link>https://www.PCBLibraries.com/forum/pqfn-pson-footprint-name_topic305_post678.html#678</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=25">JZsori</a><br /><strong>Subject:</strong> 305<br /><strong>Posted:</strong> 01 Jun 2012 at 7:05pm<br /><br />There are multiple instances with the same name and description (PSON50P400X400X80-14, for example) but one has rectangular pads and the other has D-Shape pads.&nbsp; There should be some way to differentiate.]]>
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   <pubDate>Fri, 01 Jun 2012 19:05:07 +0000</pubDate>
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