PCB Libraries Forum : Third Placement Outline https://www.PCBLibraries.com/forum/ Fri, 03 Apr 2026 17:45:12 +0000 Tue, 14 May 2019 09:33:31 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 360 https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=2482 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[Third Placement Outline : The Origin Marker and Courtyard...]]> https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10240.html#10240 Author: Tom H
Subject: 2482
Posted: 14 May 2019 at 9:33am

The Origin Marker and Courtyard are on the same layer because they are both used for placement guides and they don't go out to fabrication and assembly. 

This has been this way for the past 20 years. 

The only way to fix it in V2019.03 is to turn off the origin marker in Preferences > Drafting > Courtyard.

You can manually add an origin marker on the assembly layer, but then they would appear in the assembly drawing. 

]]> Tue, 14 May 2019 09:33:31 +0000 https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10240.html#10240 <![CDATA[Third Placement Outline : My Drafting setting are the...]]> https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10238.html#10238 Author: jmeinert
Subject: 2482
Posted: 14 May 2019 at 9:08am

My Drafting setting are the same in 2019.02 as 2018.09. It looks as though the circle of the origin is being identified as a placement outline. ]]> Tue, 14 May 2019 09:08:07 +0000 https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10238.html#10238 <![CDATA[Third Placement Outline : These are the outlines that Library...]]> https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10232.html#10232 Author: Tom H
Subject: 2482
Posted: 10 May 2019 at 12:23pm

These are the outlines that Library Expert produces and you have control in Preferences > Drafting to turn them on/off with either check boxes or by turning the line width value to 0.00. 
  1. Legend (silkscreen, trimmed around pins)
  2. Assembly (closed polygon)
  3. Component (using nominal dimensions)
  4. Terminals (where the Terminal Metal touches the pad)
  5. Courtyard
All of these go to different layers and are used for different applications. 

Only the Legend is printed on the PCB. 

The Assembly is used for a drawing. 

The Courtyard is used for placement aid. 

The Component and Terminal outlines should go on the same layer as they represent the physical package in the nominal material condition. 

]]> Fri, 10 May 2019 12:23:36 +0000 https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10232.html#10232 <![CDATA[Third Placement Outline : I am getting three placement...]]> https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10231.html#10231 Author: jmeinert
Subject: 2482
Posted: 10 May 2019 at 11:32am

I am getting three placement outlines on chips with Mentor Graphics. I get the normal courtyard and component outlines, with an additional circle in the middle of the part with placement outline and height.
 
version 2019.2
]]> Fri, 10 May 2019 11:32:21 +0000 https://www.PCBLibraries.com/forum/third-placement-outline_topic2482_post10231.html#10231