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1008 Chip Inductor Land Pattern

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Lukas View Drop Down
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    Posted: 25 Mar 2021 at 5:25pm
Hello There,

in their specifications https://www.murata.com/~/media/webrenewal/support/library/catalog/products/inductor/chip/o05e.ashx page 130 (LQM2HP_EH), murata recommends a pad width (c) of 1.5mm which is considerably less than the width of the package/metalisation of 2.0mm. I tried to find any explanation for this, as I've never seen pads smaller than the width of the package.

For capacitors, murata also recommends making the pad smaller than the width, mentioning that this reduces stress: https://www.murata.com/en-us/support/faqs/products/capacitor/ceramiccapacitor/mnt/0008

Other manufacturers of similar-sized inductors propose more reasonable looking footprints: https://media.digikey.com/pdf/Data%20Sheets/Samsung%20PDFs/CIGT252010EH2R2MNE_Spec.pdf

Are there any IPC recommendations that would call for reduced pad widths as suggested by Murata?

Best Regards

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Tom H View Drop Down
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 25 Mar 2021 at 5:54pm
The only consideration for a pad stack width to be smaller than the Terminal Lead is the Wave Solder process for bottom side mounted SMD packages. 

The IPC-7351 mathematical model includes the Terminal Lead Width and the Width Tolerance. This will always result in a pad size greater than the Terminal Width. 

However, this can be controlled by editing the solder joint "side" goals by making it a negative value. 

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