PCB Libraries Forum : PCB Design Basics https://www.PCBLibraries.com/forum/ Tue, 14 Apr 2026 08:12:34 +0000 Mon, 21 Jul 2025 00:48:53 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 30 https://www.PCBLibraries.com/forum/RSS_topic_feed.asp?FID=8 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[PCB Design Basics : Tips for Managing Footprint Libraries in PCB Desig]]> https://www.PCBLibraries.com/forum/tips-for-managing-footprint-libraries-in-pcb-desig_topic3500_post13914.html#13914 Author: getawaycar
Subject: Tips for Managing Footprint Libraries in PCB Desig
Posted: 21 Jul 2025 at 12:48am

Hi, thank you so much for taking the time to share such a detailed and informative reply!
Your points about static libraries, IPC standards, and using calculators really opened my eyes to some new approaches I hadn’t considered.
I’ll definitely look into Footprint Expert and study you shared.
Thanks again for your insights — really appreciate it!
]]> Mon, 21 Jul 2025 00:48:53 +0000 https://www.PCBLibraries.com/forum/tips-for-managing-footprint-libraries-in-pcb-desig_topic3500_post13914.html#13914 <![CDATA[PCB Design Basics : Tips for Managing Footprint Libraries in PCB Desig]]> https://www.PCBLibraries.com/forum/tips-for-managing-footprint-libraries-in-pcb-desig_topic3500_post13909.html#13909 Author: Tom H
Subject: Tips for Managing Footprint Libraries in PCB Desig
Posted: 11 Jul 2025 at 8:08am

Static CAD libraries available on in the market are problematic because you need to deal with whatever someone created. Different people use different rules and guidelines. One of the most frustrating and simple things is measurement units - Inch or Metric. 

Then there are all the Drafting Outlines. Even when you use Mfr. Recommended Patterns.
Read this: 
https://www.pcblibraries.com/forum/manufacturer-recommended-patterns_topic3449.html?FID=35&PR=3

Then there is an IPC-7351 3-Tier library system, but static libraries never offer that option. 

We recommended using 'Calculators' to autogenerate solder patterns directly from package dimensions and user defined Options for every aspect of a PCB library footprint. In a footprint Calculator, the package dimensions can be used to autogenerate a high quality 3D STEP model. 

The Calculators display the component body and terminal lead outlines, so when you use the mfr. recommended pattern, you can actually see the solder joint goals real time. 

Every non-standard semiconductor package and connector must use the mfr. recommended pattern because it's impossible to calculate a non-standard pad stack and footprint. There is only 1-Tier for non-standard packages. 

The quality control for manually building non-standard mfr. recommended patterns is to import the 3D STEP model provided by the component manufacturer to ensure all the terminal lead accuracy on the pad stacks. 

Organizing your library data in an editor that saves the package dimensions, Footprint Name, Physical Description, Case Code, Manufacturer, Part Number, Logical Description, Mounting Type, Datasheet link, Part Status and Comments is very important for long term library organization. You need a quick way to find all the parts you built over the years and eliminate duplication of effort. 

A neutral database is important on many levels. You can change your master option file and generate an entirely new library with one click. You can also change CAD tools and rebuild your library with one click. 

You can also sort through many different component manufacturers package dimensions and find common package dimensions with similar tolerances to streamline the creation of your discrete component library of Chip packages. 

Try Footprint Expert for a 30-day free trial and a webcast training and you'll see the future of electronic product development automation. 

]]> Fri, 11 Jul 2025 08:08:33 +0000 https://www.PCBLibraries.com/forum/tips-for-managing-footprint-libraries-in-pcb-desig_topic3500_post13909.html#13909 <![CDATA[PCB Design Basics : Tips for Managing Footprint Libraries in PCB Desig]]> https://www.PCBLibraries.com/forum/tips-for-managing-footprint-libraries-in-pcb-desig_topic3500_post13908.html#13908 Author: getawaycar
Subject: Tips for Managing Footprint Libraries in PCB Desig
Posted: 11 Jul 2025 at 2:27am

Hi all,

I’m currently working on improving my PCB design workflow, and I’ve noticed that managing footprint libraries can be quite time-consuming, especially when dealing with multiple component suppliers and custom parts.

I’d love to hear how other designers handle this. Do you rely mostly on manufacturer-provided footprints, build your own from scratch, or use third-party libraries?

Looking forward to your insights and best practices!

Thanks in advance!
]]> Fri, 11 Jul 2025 02:27:35 +0000 https://www.PCBLibraries.com/forum/tips-for-managing-footprint-libraries-in-pcb-desig_topic3500_post13908.html#13908 <![CDATA[PCB Design Basics : HDI Material selection]]> https://www.PCBLibraries.com/forum/hdi-material-selection_topic3243_post12891.html#12891 Author: davidM37
Subject: HDI Material selection
Posted: 02 Mar 2023 at 2:39am

Hi all,

I am interested in understanding the physical standards of HDI PCBs compared with conventional PCBs.
Typically, overall thickness for conventional PCBs can be specified from a range of standard thicknesses e.g. 0.6mm, 1.0mm, 1.6mm. Within these thicknesses a range of prepreg, cores and copper are specified to fit the functional requirements of the board.
Is there an equivalent range of overall thickness of the board that is common in HDI boards. And are there standard material configurations of copper and dielectric, of given thicknesses, to achieve these overall thicknesses?

Thanks in advance for any thought on this.

David
]]> Thu, 02 Mar 2023 02:39:28 +0000 https://www.PCBLibraries.com/forum/hdi-material-selection_topic3243_post12891.html#12891 <![CDATA[PCB Design Basics : BGA ball and ball pad on PCB can be accepted]]> https://www.PCBLibraries.com/forum/bga-ball-and-ball-pad-on-pcb-can-be-accepted_topic3177_post12632.html#12632 Author: Tom H
Subject: BGA ball and ball pad on PCB can be accepted
Posted: 14 Oct 2022 at 9:29am

Here is a BGA pad size calculation table. 


 
]]> Fri, 14 Oct 2022 09:29:47 +0000 https://www.PCBLibraries.com/forum/bga-ball-and-ball-pad-on-pcb-can-be-accepted_topic3177_post12632.html#12632 <![CDATA[PCB Design Basics : BGA ball and ball pad on PCB can be accepted]]> https://www.PCBLibraries.com/forum/bga-ball-and-ball-pad-on-pcb-can-be-accepted_topic3177_post12631.html#12631 Author: arunhoneywell.com
Subject: BGA ball and ball pad on PCB can be accepted
Posted: 14 Oct 2022 at 1:57am

Commonly, what’s maximum diameter difference between BGA ball and ball pad on PCB can be accepted? ]]> Fri, 14 Oct 2022 01:57:55 +0000 https://www.PCBLibraries.com/forum/bga-ball-and-ball-pad-on-pcb-can-be-accepted_topic3177_post12631.html#12631 <![CDATA[PCB Design Basics : Purpose of No Probe Top and DFA Top]]> https://www.PCBLibraries.com/forum/purpose-of-no-probe-top-and-dfa-top_topic3139_post12482.html#12482 Author: Tom H
Subject: Purpose of No Probe Top and DFA Top
Posted: 28 Jun 2022 at 8:35am

I'm not an expert on the Allegro CAD tool, but I am familiar with the terms. 

You would use a "No probe TOP" feature if you're using Test Points. They cannot be placed under a footprint because they need to be Probed. The No probe TOP feature throws a DRC error if a Test Point is in the No Probe area. Also, Allegro has a feature for auto-placing test points. That feature will avoid all No probe TOP areas. 

Place Bound Top is used to establish a part placement area. You set spacing rules for each component footprint. If you violate the Place Bound spacing rules Allegro throws a DRC error. Other CAD tools that have less features use a Placement Courtyard boundary outline as a guide for part placement. 

]]> Tue, 28 Jun 2022 08:35:15 +0000 https://www.PCBLibraries.com/forum/purpose-of-no-probe-top-and-dfa-top_topic3139_post12482.html#12482 <![CDATA[PCB Design Basics : Purpose of No Probe Top and DFA Top]]> https://www.PCBLibraries.com/forum/purpose-of-no-probe-top-and-dfa-top_topic3139_post12481.html#12481 Author: ANANDT
Subject: Purpose of No Probe Top and DFA Top
Posted: 27 Jun 2022 at 9:13pm

Hi,

I'm currently working with Allegro, please explain the purpose of No probe TOP why do we need to add one for our footprint. 

Next if we create a standard footprint using Allegro Footprint wizard it creates Place Bound Top along with DFA Top how one differs from another and purpose of it. 

Please explain.

]]> Mon, 27 Jun 2022 21:13:07 +0000 https://www.PCBLibraries.com/forum/purpose-of-no-probe-top-and-dfa-top_topic3139_post12481.html#12481 <![CDATA[PCB Design Basics : Metric PCB Design Tips]]> https://www.PCBLibraries.com/forum/metric-pcb-design-tips_topic3103_post12372.html#12372 Author: Tom H
Subject: Metric PCB Design Tips
Posted: 14 Apr 2022 at 9:16am

Congratulations! You'll find out really quick that themetric system is superior to imperial units.

I have a personal guarantee that if you use these rulesand do 5 PCB designs in metric, it will be impossible for you to switch back toimperial, because you will discover the beauty of the metric system and theugliness of the imperial system.

Here are the things you need to be concerned about:

  1. Make sure your PCB Library is completely created in metric units. Mixing imperial unit footprints in a metric PCB layout is very messy.
  1. It’s best that your Board Outline is in metric units, but that’s up to the mechanical engineer.
  1. Make all Mounting Hole pad and drill sizes in 0.05 increments. Placement grid is up to the mechanical engineer.
  1. Create all your PCB design elements in 0.05 mm increments.
    1. Library parts

                                                              i.     Line Width and Gap for Silkscreen 0.15

                                                            ii.     Line Width for Assembly 0.10

                                                          iii.     Line Width for Courtyard 0.05

                                                          iv.     SMD Pad Length & Width

                                                            v.     Pad placement

                                                          vi.     PTH pad and hole diameters

                                                         vii.     Note: the worst metric SOP/QFP/QFN/SON is a 0.65mm pitch. This screws up a great PCB layout. Be on the lookout. 

    1. Part Placement – use numbers in 0.10 mm increments

                                                              i.     Big parts snap to 1.00 mm grid

                                                            ii.     Medium parts snap to 0.50 mm grid

                                                          iii.     Small parts snap to 0.10 mm grid

    1. Routing traces – use 0.05 mm increments

                                                              i.     Best Signal Trace Width = 0.10 mm – this allowsdifferential pairs for a 1.00 mm pitch BGA

                                                            ii.     Power Trace Widths = 0.20, 0.30, 0.40, 0.50,etc.

                                                          iii.     Routing Grid = 0.05 mm

                                                          iv.     Via Pad Size = 0.50 & Via Hole Size = 0.25

                                                            v.     SMD Via Fanout should snap to a 0.10 mm grid ifpossible

]]> Thu, 14 Apr 2022 09:16:59 +0000 https://www.PCBLibraries.com/forum/metric-pcb-design-tips_topic3103_post12372.html#12372 <![CDATA[PCB Design Basics : PCB Design Problem]]> https://www.PCBLibraries.com/forum/pcb-design-problem_topic3102_post12371.html#12371 Author: ROSELJR
Subject: PCB Design Problem
Posted: 13 Apr 2022 at 7:14pm

In the PCB design editing interface, the following shortcut keys: PL, PT, PI, PM start the line drawing (under the bottom layer layer), each adapting to the nature of the connection.

https://www.utmel.com/blog/categories/pcb/hf-pcb-circuit-design-10-questions

]]> Wed, 13 Apr 2022 19:14:24 +0000 https://www.PCBLibraries.com/forum/pcb-design-problem_topic3102_post12371.html#12371