PCB Libraries Forum : Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA https://www.PCBLibraries.com/forum/ Sun, 19 Apr 2026 03:08:30 +0000 Fri, 12 Feb 2021 09:01:01 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 360 https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=2815 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA : I have the following definitions...]]> https://www.PCBLibraries.com/forum/difference-prohibit-via-hole-and-prohibit-via_topic2815_post11214.html#11214 Author: Tom H
Subject: 2815
Posted: 12 Feb 2021 at 9:01am

I have the following definitions for you:

- Via Keepout: prevents a via being placed on that layer.
- Via Hole Keepout: allows a via to be stop on that layer, but prevents it passing through the dielectric layer below that layer.

As Via Hole Keepout prevents a via from going through the dielectric layer below it, it is not valid for the bottom layer due to having no dielectric layer below.

This function was not available in the older CADSTAR.

Best regards / Mit freundlichen Grüßen
 
Karl-Heinz Kluwetasch
Geschäftsführender Gesellschafter  |  Chief Executive Officer

]]> Fri, 12 Feb 2021 09:01:01 +0000 https://www.PCBLibraries.com/forum/difference-prohibit-via-hole-and-prohibit-via_topic2815_post11214.html#11214 <![CDATA[Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA : Hello all,Can someone explain...]]> https://www.PCBLibraries.com/forum/difference-prohibit-via-hole-and-prohibit-via_topic2815_post11212.html#11212 Author: Olaf.MuellerAE
Subject: 2815
Posted: 10 Feb 2021 at 2:04am

Hello all,

Can someone explain me the difference between PROHIBIT_VIA and PROHIBIT_VIA_HOLE?

These keep-out layers come up during eCADSTAR export.

For me each PROHIBIT_VIA is also a PROHIBIT_VIA_HOLE. I see no sense for a single PROHIBIT_VIA_HOLE area.

Best Regards,
Olaf
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