The Chip Package is the most widely used in the electronicsindustry. Chip components have an average of 80% of the total parts on atypical PCB assembly. Here is an image of the average chip terminal lead form.

Let’s compare the differences between IPC-J-STD-001 andIPC-7351B standards.

IPC-J-STD-001 uses 3 classes to define solder joint goalacceptability for various electronic products.

CLASS 1 –General Electronic Products

Includes products suitable for applications where the majorrequirement is function of the completed assembly. Toys

CLASS 2 –Dedicated Service Electronic Products

Includes products where continued performance and extendedlife is required, and for which uninterrupted service is desired but notcritical. Typically, the end-use environment would not cause failures.Computers & Phones

CLASS 3 –High Performance Electronic Products

Includes products where continued high performance orperformance-on-demand is critical, equipment downtime cannot be tolerated,end-use environment may be uncommonly harsh, and the equipment must functionwhen required, such as life support or other critical systems. Military &Medical

IPC-J-STD-001 defines the requirements for electronicassemblies. Land pattern footprint pad sizes and locations play a significantrole in meeting these requirements. The IPC-7351 guideline falls underJ-STD-001 to define the solder joint goals for Toe, Heel and Side values andthe land pattern and pad stack naming conventions.

The footprint pad size is determined by the terminal leadsize, the terminal lead tolerances, the manufacturing tolerances forfabrication and assembly and the Toe, Heel and Side solder joint goals asdefined in the IPC-7351 guideline.

The Toe solder joint goal is the most important for the ChipTerminal Lead and the J-STD-001 Minimum Fillet Height for a Chip Component forthe Toe Goal is:

The Fdimension for Toe Fillet for Class 1 & Class 2 Fabrication is:

• Wetting is evident on the vertical surface of the componentterminal

The Fdimension for Toe Fillet for Class 3 Fabrication is:

• (G) + 25%(H) or (G) + 0.5 mm, whichever is less

Example: For Class 3, let’s say that the 0805 Chip Capacitoris 4.00 mm height. 25% of 4 = 1.00 mm. But the IPC-J-STD-001 standard says the0.50 mm is an acceptable solder fillet height because it’s less than 1.00 mm.But what about an 01005 chip resistor with a 0.13 mm height? Using a 0.075stencil thickness, J-STD-001 recommends a Toe fillet of (G) 0.07 + 25% (H) 0.03mm = 0.10 mm. But (G) is actually less than 0.05 mm after reflow.

If the Toe pad length is too long, there will be excessivesolder. When going into a reflow oven, if there is excessive solder and pin 1hits the heat first, the excessive solder will melt and pull the chip up into atombstone position. To eliminate tombstoning, the pad Toe must not exceed theJ-STD-001 requirements.

Here are the IPC-7351B tables for all chip packages includingResistors, Capacitors, Diodes, Inductors, Antennas, Ferrite Beads, Filters,Fuses, LED’s, Thermistors and Varistors for 3 density levels, Most, Nominal andLeast pad size.

Note that for all chips longer than a 0603, the Nominal Toevalue is 0.35 mm for 0603, 0805, 1206, 1210, 1812, 2010 and 2512, regardless oftheir height. And for every chip package less than 0603 the Nominal Toe valueis 0.20 for 03015, 01005, 0201 and 0402. Also note that the difference betweendensity levels for chips larger than 0603 is +/- 0.20 mm for Most and Least densitylevels and chips smaller than 0603 have a +/- 0.10 mm difference between Mostand Least density levels.

PCB Libraries, Inc. has a philosophy that every chip sizeshould have a unique Toe value that is aligned with J-STD-001 mathematicalmodel for the acceptable solder joint.

Here is a table for the default values in Library Expert,but all of these settings are user definable to best meet your assemblyattachment requirements. Also note that there is a +/- 0.10 mm between Most andLeast density levels for all chips.

PCB Libraries, Inc. refers to this concept as “IncrementalPad Stacks” for the sole purpose of achieving the best solder joint goals inthe assembly process. You can download the entire Library Expert Solder JointGoals Excel spreadsheet here – www.pcblibraries.com/downloadsor if you’re using Library Expert, the Excel spreadsheet is on your computer inthis folder - C:\Program Files (x86)\PCB Libraries\Library Expert2019\Documents\Library Expert Solder Joint Goal Tables.xlsx

Note that there are negative values for some Heel and Sidesolder joints. This is to compensate for the Fabrication and Assembly Tolerances(approximately 0.04 to 0.05 mm) in the IPC-7351 mathematical model. TheFabrication and Assembly Tolerances have been part of the IPC mathematicalmodel since 1987. In the past 33 years, the fabrication and assembly processeshave been improved so much that these tolerances are no longer applicable totodays advanced machines. Also, most fabrication shops swell the outer layersto compensate for their etching process. Adding an additional fabrication toleranceto the pad size calculation is a “Double (duplicate) Tolerance” and is unnecessary.

We recommended that the Fabrication and Assembly Tolerancesbe turned off to 0.00 and all negative solder joint goals also be turned to0.00. This would give the user much better control of the pad stack calculation.But this is an individual choice that every company must make on their own. Wehope that the unreleased IPC-7351C will make this adjustment to themathematical model.

It’s also important to note that Lead Solder flows muchbetter than Lead-Free Solder. Here is an image of a chip with lead solder. Youcan visually see that the solder flows from the pad Toe up the side of the chipterminal. Also note that the pad Heel is 0.00 and flush with the chip terminal.

Here is an image of chips using Lead-Free solder. Most ofthe solder just stays on the pad and does not flow up the side of the chip terminallead like Lead Solder. Also, this example illustrates excessive pad Toe. This consumesimportant PCB real estate, wastes solder and does nothing to add to the solderjoint quality.