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   <title><![CDATA[SIP-4L, Diodes : Thank you. ]]></title>
   <link>https://www.PCBLibraries.com/forum/sip4l-diodes_topic1466_post5938.html#5938</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=10849">saidzaky</a><br /><strong>Subject:</strong> 1466<br /><strong>Posted:</strong> 16 Nov 2014 at 8:28am<br /><br />Thank you.<br>]]>
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   <pubDate>Sun, 16 Nov 2014 08:28:20 +0000</pubDate>
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   <title><![CDATA[SIP-4L, Diodes : I forgot to mention that the FP...]]></title>
   <link>https://www.PCBLibraries.com/forum/sip4l-diodes_topic1466_post5905.html#5905</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 1466<br /><strong>Posted:</strong> 06 Nov 2014 at 8:59am<br /><br /><p>I forgot to mention that the FP Designer can do Oblong through-hole pad shape to avoid pad overlap and still provide a good solder joint. </p><p><br></p>]]>
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   <pubDate>Thu, 06 Nov 2014 08:59:52 +0000</pubDate>
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   <title><![CDATA[SIP-4L, Diodes : I would use FP Designer to create...]]></title>
   <link>https://www.PCBLibraries.com/forum/sip4l-diodes_topic1466_post5904.html#5904</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 1466<br /><strong>Posted:</strong> 06 Nov 2014 at 8:56am<br /><br /><p>I would use FP Designer to create this part in 3 minutes. </p><p>In V2015.02 there are no 3-Teirs for through-hole. </p><p>IPC disqualified the IPC-7251 through-hole 3-Teir library system. </p><p>Read this - </p><p><a href="http://www.pcblibraries.com/forum/ipc7251-3teir-pth-pad-stack-obsolete_topic1463.html" target="_blank" rel="nofollow">http://www.pcblibraries.com/forum/ipc7251-3teir-pth-pad-stack-obsolete_topic1463.html</a></p>]]>
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   <pubDate>Thu, 06 Nov 2014 08:56:02 +0000</pubDate>
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   <title><![CDATA[SIP-4L, Diodes : We are working to develop footprint model...]]></title>
   <link>https://www.PCBLibraries.com/forum/sip4l-diodes_topic1466_post5902.html#5902</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=10849">saidzaky</a><br /><strong>Subject:</strong> 1466<br /><strong>Posted:</strong> 06 Nov 2014 at 7:41am<br /><br /><div><span style="line-height: 1.4;">We are working to develop footprintmodel for SIP-4L using 2014.12 version and need to&nbsp;</span>build<span style="line-height: 1.4;">&nbsp;it for Eagle, it would be great if you could help me.</span></div><div><p ="ms&#111;normal"=""><o:p></o:p></p><p ="ms&#111;normal"=""><span style="line-height: 1.4;">this package has 1.27mm pin pitch and its terminal&nbsp; dimensions (0.44 Max &amp; 0.41 Max) mm, there are more details in package drawing in page #5 in this datasheet -&nbsp;<span style="line-height: 1.4;"><a href="http://www.diodes.com/datasheets/AH276Q.pdf" target="_blank" rel="nofollow">www.diodes.com/datasheets/AH276Q.pdf</a> </span></span></p><p ="ms&#111;normal"=""><span style="line-height: 1.4;">In this case, the Padstack wouldbe c145h85 but the issue is the Padstacks are overlapped&nbsp;</span></p><p ="ms&#111;normal"=""><o:p></o:p></p><p ="ms&#111;normal"="">What are the right padstackdimensions (for L, N, M)?<o:p></o:p></p><p ="ms&#111;normal"=""><br></p></div>]]>
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   <pubDate>Thu, 06 Nov 2014 07:41:31 +0000</pubDate>
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