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   <title><![CDATA[Questions &amp; Answers : Chip Caps and Resistor w/No Terminal Tolerance]]></title>
   <link>https://www.PCBLibraries.com/forum/chip-caps-and-resistor-w-no-terminal-tolerance_topic3627_post14482.html#14482</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Chip Caps and Resistor w/No Terminal Tolerance<br /><strong>Posted:</strong> 11 Mar 2026 at 8:31am<br /><br /><div>When L and L1 dimensions are the same, only enter L (don't enter duplicate dimensions).&nbsp;</div><div><br></div><div>L1 is optional if it's different than L.&nbsp;</div><div><br></div>I recommend that you open the free SM Discrete.fpx file and sort the Case Code Column.&nbsp;<div><br></div><div>Then search for similar Case Codes from other manufacturers and see what their Terminal Lead Tolerances are.&nbsp;</div><div><br></div><div>Sometimes the component manufacturer will only provide the Minimum dimension and you need to figure out the Maximum dimension.&nbsp;</div><div><br></div><div>Average Terminal Tolerances for chip components by Case Code:</div><div><ul><li>01005 - 0.03</li><li>0201 - 0.05</li><li>0402 - 0.10</li><li>0603 - 0.15</li><li>0805 - 0.20</li><li>1206 - 0.25</li><li>1812 - 0.30</li></ul><div><br></div></div>]]>
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   <pubDate>Wed, 11 Mar 2026 08:31:10 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Chip Caps and Resistor w/No Terminal Tolerance]]></title>
   <link>https://www.PCBLibraries.com/forum/chip-caps-and-resistor-w-no-terminal-tolerance_topic3627_post14480.html#14480</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=18320">pcbfreedomcad</a><br /><strong>Subject:</strong> Chip Caps and Resistor w/No Terminal Tolerance<br /><strong>Posted:</strong> 11 Mar 2026 at 5:14am<br /><br />What is entered in the tool for L and L1, when there is no tolerance for lead length given in the datasheet?&nbsp;<div><br></div><div>I am thinking of Chip Capacitor and Resistor terminal tolerances.&nbsp;</div><div><br></div>]]>
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   <pubDate>Wed, 11 Mar 2026 05:14:19 +0000</pubDate>
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   <title><![CDATA[Standard Components : Assembly Polarity Markings &amp; Scaling]]></title>
   <link>https://www.PCBLibraries.com/forum/assembly-polarity-markings-scaling_topic3625_post14478.html#14478</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Assembly Polarity Markings &amp; Scaling<br /><strong>Posted:</strong> 10 Mar 2026 at 7:36pm<br /><br /><p ="ms&#111;normal"="" style="margin-bottom:0in">The assembly pin 1 polarity markingsinclude a Dot, Circle, Chamfer and Bar.&nbsp;</p><p ="ms&#111;normal"="" style="margin-bottom:0in">Polarity indicators scalethemselves to the part size within defined user or hard-coded minimum and maximumlimits.</p><p ="ms&#111;normal"="" style="margin-bottom:0in">The <i>dot and circle</i> sizesare equal to 1/2 the lesser of body length or width, not to exceed the circle/dotminimum and maximum limits.</p><p ="ms&#111;normal"="" style="margin-bottom:0in">Here are the Options for settingthe minimum &amp; maximum assembly polarity Circle/Dot sizes.<o:p></o:p></p><p ="ms&#111;normal"="" style="margin-bottom:0in"><img src="uploads/3/Assembly_Polarity_Min-Max_Opti&#111;ns.png" height="367" width="487" border="0" /><br></p><p ="ms&#111;normal"="" style="margin-bottom:0in">The Circle/Dot sizes automaticallyscale per the minimum body dimension.</p><p ="ms&#111;normal"="" style="margin-bottom:0in">Here is a sample of an Assembly PolarityCircle:<o:p></o:p></p><p ="ms&#111;normal"="" style="margin-bottom:0in"><img src="uploads/3/Assembly_Polarity_Circle.png" height="336" width="352" border="0" /><br></p><p ="ms&#111;normal"="" style="margin-bottom:0in">Here is a sample of an Assembly PolarityCircle:</p><p ="ms&#111;normal"="" style="margin-bottom:0in"><img src="uploads/3/Assembly_Polarity_Dot_2026-03-10_19-31-13.png" height="339" width="355" border="0" /><br></p><p ="ms&#111;normal"="" style="margin-bottom:0in">The <i>Chamfer</i> is equal to 1/3the lesser of body dimension and not to exceed a maximum of 1.00 mm.&nbsp;</p><p ="ms&#111;normal"="" style="margin-bottom:0in">Example:if the minimum body dimension is 1.60 mm, the chamfer size will be 1/3 less or 0.53mm.</p><p ="ms&#111;normal"="" style="margin-bottom:0in">Here is a sample of an Assembly PolarityChamfer:<o:p></o:p></p><p ="ms&#111;normal"="" style="margin-bottom:0in"><img src="uploads/3/Assembly_Polarity_Chamfer.png" height="336" width="353" border="0" /><br></p><p ="ms&#111;normal"="" style="margin-bottom:0in">The <i>Polarity Bar</i> is equalto 1/6 the package body width, not less than 0.25 mm or more than 1mm max. ThePolarity Bar is limited to polarized 2-pin packages including Capacitors,Diodes, LEDs and Antennas.</p><p ="ms&#111;normal"="" style="margin-bottom:0in">Here is a sample of an Assembly Polarity Bar:<o:p></o:p></p><p ="ms&#111;normal"="" style="margin-bottom:0in"><img src="uploads/3/Assembly_Polarity_Bar.png" height="279" width="606" border="0" /><br></p><p ="ms&#111;normal"="" style="margin-bottom:0in">You select the type of assembly polarity marking and it will be applied to all your footprint patterns.&nbsp;</p><p ="ms&#111;normal"="" style="margin-bottom:0in">This will add consistency to your PCB library assembly polarity markings.&nbsp;</p><p ="ms&#111;normal"="" style="margin-bottom:0in"><br></p><p ="ms&#111;normal"="" style="margin-bottom:0in"><o:p></o:p></p>]]>
   </description>
   <pubDate>Tue, 10 Mar 2026 19:36:54 +0000</pubDate>
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   <title><![CDATA[Version History : Footprint Expert 26.03 Released!!]]></title>
   <link>https://www.PCBLibraries.com/forum/footprint-expert-26-03-released_topic3624_post14477.html#14477</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1">Nick B</a><br /><strong>Subject:</strong> Footprint Expert 26.03 Released!!<br /><strong>Posted:</strong> 09 Mar 2026 at 11:08am<br /><br /><a href="http://www.pcblibraries.com/downloads" target="_blank" rel="nofollow"><font color="#0066cc"><u>Version 26.03 was just released</u></font></a>!!<p dir="ltr" style="margin-right: 0px;"><img src="https://www.pcblibraries.com/Forum/uploads/1/PCBLDVDDownloadNow26.png" height="275" width="204" border="0" /></p><div><p ="ms&#111;normal"=""><b><u>Fixes &amp; Enhancements:</u></b></p><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">3D STEP:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Update Polarized Chip Capacitor</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">KiCad - terminal outlines are not registering correctly on the pads</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">FP Designer:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Adding a Paste Mask Layer to a through-hole pad stack for Pin-in-Paste added it twice in the Pad Stack Manager</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">BGA automatic alphanumeric pin numbers start repeating at 'BA' after 'BY'</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">When Drafting &gt; Silkscreen &gt; Allow Expanded Outline was turned off, the Save to FPX would not turn on</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Remove the word Flat from the SON and PSON in Specifications &gt; Description Category list</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Library Editor:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Right Mouse &gt; Add New Rows &gt; 2. If you change the number of rows from 2 to 1 the program added 2&nbsp;</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Utilities &gt; Find Duplicate Part Numbers was displaying one less found item than reality</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Remove the word Flat from the SON and PSON Physical Description in the FPX file&nbsp;</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Options:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Pad stack name was adding redundant Mask pads shape identifier (C, R, etc.) if it is the same as the top pad shape</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">SMD Pad Stack Rules &gt; Thermal Tabs</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Added Thermal Tab Minimum Pattern to Pad Edge</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Added ability to corner radius thermal pad paste mask apertures</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">The SOIC/SOP component family zero orientation was not communicating to the Calculator</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Added ability to corner radius thermal pad paste mask apertures</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Components &gt; Surface Mount &gt; DPAK &gt; Thermal Tab Paste Mask Shape &gt; 'Pattern' is the new default</li></ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Calculators:</li><ul><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Added reconciliation for 2 pin parts with dissimilar terminal sizes and tolerances (keeps calculation the same when pin locations are reversed)</li><li ="ms&#111;normal"="" style="margin-bottom: 0in;">Surface Mount &gt; DPAK &gt; Paste Mask – 'Simple' now follows the Paste Mask Reduction % set in Options</li></ul></ul><div><br></div></div>]]>
   </description>
   <pubDate>Mon, 09 Mar 2026 11:08:17 +0000</pubDate>
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   <title><![CDATA[Options : Footprint Too Small For Silkscreen Outline]]></title>
   <link>https://www.PCBLibraries.com/forum/footprint-too-small-for-silkscreen-outline_topic3623_post14476.html#14476</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Footprint Too Small For Silkscreen Outline<br /><strong>Posted:</strong> 08 Mar 2026 at 12:16pm<br /><br /><p ="ms&#111;normal"="">Question: How does the silkscreen spacing option considerpads are too close?<o:p></o:p></p><p ="ms&#111;normal"="">Example of a trimming rule: the<b> Calculator</b> trims padsizes for you when they fail to meet the specifications in Rules.&nbsp; Thedefault values we use are all considered best industry practice. <o:p></o:p></p><p ="ms&#111;normal"="">Note: pad clearances are not guaranteed for <b>FP Designer </b>footprintsand there are no warnings.<o:p></o:p></p><p ="ms&#111;normal"=""><img src="uploads/3/Minimum_Trim_Settings.png" height="437" width="396" border="0" /><br></p><p ="ms&#111;normal"="">The clearance of the silkscreen to the body and any pads isset in the <b><i>Drafting &gt; Silkscreen</i></b> options. The silkscreen isautomatically trimmed, if required, to meet these values.</p><p ="ms&#111;normal"=""><img src="uploads/3/Silkscreen_Clearance_Opti&#111;ns.png" height="158" width="334" border="0" />&nbsp;<o:p></o:p></p><p ="ms&#111;normal"="">There is a hard-coded minimum silkscreen line length of <b><i>3silkscreen line widths</i></b><i>.</i>&nbsp; Any silkscreen line segment lessthan this length is removed to avoid the appearance of ‘specks’ on a PCB. <o:p></o:p></p><p ="ms&#111;normal"=""></p><p ="ms&#111;normal"="">Here is a 0603 chip capacitor that has enough pad-to-padspacing to allow a silkscreen line. This silkscreen outline length exceeds 3line widths.</p><p ="ms&#111;normal"=""><img src="uploads/3/Resistor_with_Silkscreen_3.png" height="294" width="635" border="0" /><br></p><p ="ms&#111;normal"="">Here is a 0603 chip capacitor that violates the pad-to-padspacing to allow a silkscreen line. The silkscreen outline wraps around thepads and the courtyard outline is pushed out to include the expanded silkscreenoutline.</p><p ="ms&#111;normal"=""><img src="uploads/3/Resistor_with_Expanded_Silkscreen.png" height="338" width="669" border="0" />&nbsp;</p><p ="ms&#111;normal"=""></p><p ="ms&#111;normal"="">You have options to turn off the silkscreen outline if thepattern is too small to create one.</p><p ="ms&#111;normal"=""><img src="uploads/3/Allow_Expanded_Silkcreen_Outline.png" height="354" width="505" border="0" />&nbsp;<o:p></o:p></p><p ="ms&#111;normal"="">You can also turn off the courtyard excess for including thesilkscreen outline.<o:p></o:p></p><p ="ms&#111;normal"=""><img src="uploads/3/Expand_Courtyard_to_Include_Silkscreen.png" height="307" width="494" border="0" /><br></p><p ="ms&#111;normal"="">&nbsp;</p><p ="ms&#111;normal"=""><br></p>]]>
   </description>
   <pubDate>Sun, 08 Mar 2026 12:16:50 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Thermal Pad and Paste Mask Apertures]]></title>
   <link>https://www.PCBLibraries.com/forum/thermal-pad-and-paste-mask-apertures_topic3622_post14475.html#14475</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Thermal Pad and Paste Mask Apertures<br /><strong>Posted:</strong> 05 Mar 2026 at 7:39am<br /><br />All out Texas Instruments footprints on <a href="https://www.pcblibraries.com/POD" target="_blank" rel="nofollow">www.pcblibraries.com/POD</a> that have thermal pads, have the exact checkerboard pattern dimensions and spacing as their datasheets provide. Including 0.05 mm corner radius.&nbsp;<div><br></div><div>These parts include QFN, SON, QFP, SOP, PSON, PQFN, DPAK with thermal pads. There are approximately 40,000 TI footprints with thermal pads on the Parts on Demand cloud database.&nbsp;</div><div><br></div><div>The only way to accomplish this is to build the footprint using the calculator and setup all the TI package and footprint dimensions and save to FPX for the 3D STEP model.&nbsp;</div><div><br></div><div>Then move the footprint to FP Designer for customizing the paste mask apertures in the thermal pad stack. Then save to FPX as the real footprint.&nbsp;</div><div><br></div><div>Rename the Calculator footprint and Physical Description to match the FP Designer data.&nbsp;</div><div><br></div><div>Output to CAD the FP Designer footprint footprint first. Then open the Calculator footprint and create the 3D STEP only and overwrite the FP Designer 3D STEP model.&nbsp;</div><div><br></div><div>Then import into your CAD tool and you'll get the perfect mfr. recommended pattern with a high-quality 3D STEP model.&nbsp;</div><div><br></div>]]>
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   <pubDate>Thu, 05 Mar 2026 07:39:00 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Thermal Pad and Paste Mask Apertures]]></title>
   <link>https://www.PCBLibraries.com/forum/thermal-pad-and-paste-mask-apertures_topic3622_post14474.html#14474</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=18320">pcbfreedomcad</a><br /><strong>Subject:</strong> Thermal Pad and Paste Mask Apertures<br /><strong>Posted:</strong> 05 Mar 2026 at 3:19am<br /><br />If a bottom pad of a QFN for example, has multiple paste mask openings generated from PCB Libraries, do these openings need to have rounded corners, or do the fabricators handle the issue with 90 degree corners on stencil openings automatically?<div><div><br></div><div>I know the bottom pad itself can have rounded corners.</div></div>]]>
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   <pubDate>Thu, 05 Mar 2026 03:19:41 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : PCB Model Select Radial (Dipped) Rect. 1]]></title>
   <link>https://www.PCBLibraries.com/forum/pcb-model-select-radial-dipped-rect-1_topic3605_post14461.html#14461</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=11979">m.elsayed</a><br /><strong>Subject:</strong> PCB Model Select Radial (Dipped) Rect. 1<br /><strong>Posted:</strong> 24 Feb 2026 at 4:40am<br /><br /><div style=": rgb251, 251, 253;">you mean we can you Radial (Dipped) Rect for this part&nbsp; <span style="font-size: 14px;">For this part” 224MKP275KBG4” in this datasheet “"</span></div><div style=": rgb251, 251, 253;"><span style="font-size: 14px;"><br></span></div><div style=": rgb251, 251, 253;"><span style="font-size: 14px;"><a href="http://download.silic&#111;nexpert.com/pdfs2/2023/5/12/0/10/38/943385/cde_/manual/mkp.pdf" target="_blank" rel="nofollow">http://download.siliconexpert.com/pdfs2/2023/5/12/0/10/38/943385/cde_/manual/mkp.pdf</a></span></div><div>please add more details why should use fp designer</div>]]>
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   <pubDate>Tue, 24 Feb 2026 04:40:07 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : PCB Model Select Radial (Dipped) Rect. 1]]></title>
   <link>https://www.PCBLibraries.com/forum/pcb-model-select-radial-dipped-rect-1_topic3605_post14457.html#14457</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> PCB Model Select Radial (Dipped) Rect. 1<br /><strong>Posted:</strong> 15 Feb 2026 at 11:47am<br /><br />We recommend that if the Radial (Dipped) Rect. w/Offset Leads 3D STEP does not look correct, then build the footprint from scratch in FP Designer.&nbsp;<div><br></div>]]>
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   <pubDate>Sun, 15 Feb 2026 11:47:23 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : PCB Model Selection Confirm - Molded Body]]></title>
   <link>https://www.PCBLibraries.com/forum/pcb-model-selection-confirm-molded-body_topic3600_post14456.html#14456</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> PCB Model Selection Confirm - Molded Body<br /><strong>Posted:</strong> 15 Feb 2026 at 11:45am<br /><br />If D1 is less than 0.60 then start in the Molded Body calculator with most of the dimensions and the mfr. recommended pattern.&nbsp;<div><br></div><div>Then move the footprint to FP Designer and fill out the 'Specifications' panel and edit the Body dimensions and pad stacks as needed.&nbsp;</div><div><br></div>]]>
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   <pubDate>Sun, 15 Feb 2026 11:45:00 +0000</pubDate>
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